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W83627THF W83627THG Winbond LPC I/O
Date:
Sep. 26, 2006
Revision: 1.22
W83627THF/W83627THG
W83627THF/W83627THG Data Sheet Revision History
PAGES DATES VERSION WEB VERSION MAIN CONTENTS
1 2 3 4 5 6 7 8 9 10 11
N.A. P.104 P.117~120 P.116~122 P.7 P.18 P.8
01/16/2003 03/25/2003 04/10/2003 08/05/2003 02/16/2004 03/09/3002
0.50 0.60 0.70 0.80 0.81 0.90 1.0 1.1 1.2 1.21 1.22
First published preliminary version. SUSLED data correction. Add Item 7.8.9 Update Appendix A to demo circuit Add Block Diagram Add description for GP26(Pin93) Modify PIN CONFIGURATION Update VCN and APN in Chapter 13,14. Add lead-free part number --W83627THG Correct typo at Chapter 14.. Add description on GP40(pin 75). Correct pin configuration. Add DC characteristics.
P.116
07/22/04 11/09/04
P.19 P.8 P.8
01/19/05 04/13/05 09/26/2006
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
Table of Contents1. GENERAL DESCRIPTION................................................................................................................. 1 2. FEATURES ........................................................................................................................................ 3 3. PIN DESCRIPTION............................................................................................................................ 8 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 LPC Interface ........................................................................................................................... 9 FDC Interface......................................................................................................................... 10 Multi-Mode Parallel Port......................................................................................................... 11 Serial Port Interface ............................................................................................................... 13 KBC Interface......................................................................................................................... 14 Hardware Monitor Interface ................................................................................................... 14 Game Port.............................................................................................................................. 15 General Purpose I/O Port ...................................................................................................... 15
3.8.1 3.8.2 3.8.3 3.8.4 General Purpose I/O Port 1 (Power source is Vcc)..........................................................................15 General Purpose I/O Port 2 (Power source is Vcc)..........................................................................16 General Purpose I/O Port 3, 4 (Power source is VSB) ....................................................................16 General Purpose I/O Port 5 (Power source is VCC) ........................................................................17
3.9
POWER PINS ........................................................................................................................ 18
3.10 GPIO PIN Power Source ....................................................................................................... 18 4. GENERAL PURPOSE I/O................................................................................................................ 19 5. HARDWARE MONITOR .................................................................................................................. 21 5.1 5.2 5.3 General Description ............................................................................................................... 21 Access Interface..................................................................................................................... 21 Analog Inputs ......................................................................................................................... 23
5.3.1 Monitor over 4.096V voltage: ...........................................................................................................24 5.3.2 CPUVCORE voltage detection method: ..........................................................................................24 5.3.3 Temperature Measurement Machine...............................................................................................25
5.4
FAN Speed Count and FAN Speed Control .......................................................................... 26
5.4.1 Fan speed count ..............................................................................................................................26 5.4.2 Fan speed control ............................................................................................................................28
5.5
SmartFanTM Control ............................................................................................................... 28
5.5.1 Thermal Cruise mode ......................................................................................................................29 5.5.2 Fan Speed Cruise mode..................................................................................................................30 5.5.3 Manual Control Mode ......................................................................................................................31
5.6
SMI# interrupt mode............................................................................................................... 31
5.6.1 Voltage SMI# mode : .......................................................................................................................31 5.6.2 Fan SMI# mode : .............................................................................................................................31 5.6.3 The W83627THF temperature sensor 1(SYSTIN) SMI# interrupt has 3 modes: .............................32 5.6.4 The W83627THF temperature sensor 2(CPUTIN) and sensor 3(AUXTIN) SMI# interrupt has two modes and it is programmed at CR[4Ch] bit 6. ...........................................................................................33
5.7
OVT# interrupt mode.............................................................................................................. 34
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W83627THF/W83627THG
5.8 REGISTERS AND RAM......................................................................................................... 35
5.8.1 Address Port (Port x5h) ...................................................................................................................35 5.8.2 Data Port (Port x6h).........................................................................................................................35 5.8.3 Configuration Register Index 40h................................................................................................36 5.8.4 Interrupt Status Register 1 Index 41h...........................................................................................37 5.8.5 Interrupt Status Register 2 Index 42h..........................................................................................37 5.8.6 SMI# Mask Register 1 Index 43h ................................................................................................38 5.8.7 SMI# Mask Register 2 Index 44h ................................................................................................38 5.8.8 Reserved Register Index 45h--46h ............................................................................................39 5.8.9 Fan Divisor Register I Index 47h .................................................................................................39 5.8.10 Value RAM Index 20h- 3Fh .........................................................................................................39 5.8.11 Device ID Register - Index 49h ........................................................................................................41 5.8.12 5.8.13 5.8.14 5.8.15 5.8.16 5.8.17 5.8.18 5.8.19 5.8.20 5.8.21 5.8.22 5.8.23 5.8.24 5.8.25 5.8.26 5.8.27 5.8.28 5.8.29 5.8.30 5.8.31 5.8.32 5.8.33 5.8.34 5.8.35 5.8.36 5.8.37 5.8.38 5.8.39 5.8.40 5.8.41 5.8.42 Reserved Register Index 4Ah .....................................................................................................41 Fan Divisor Register II - Index 4Bh ..................................................................................................41 SMI#/OVT# Control Register- Index 4Ch.........................................................................................42 FAN IN/OUT and BEEP Control Register- Index 4Dh......................................................................42 Register 50h ~ 5Fh Bank Select Register - Index 4Eh ....................................................................43 Winbond Vendor ID Register - Index 4Fh ........................................................................................44 Winbond Test Register -- Index 50h - 55h (Bank 0).........................................................................44 BEEP Control Register 1-- Index 56h (Bank 0)................................................................................44 BEEP Control Register 2-- Index 57h (Bank 0)................................................................................45 Chip ID -- Index 58h (Bank 0) ..........................................................................................................46 Diode Selection Register -- Index 59h (Bank 0) ............................................................................46 Reserved -- Index 5Ah (Bank 0) ......................................................................................................47 Reserved -- Index 5Bh (Bank 0) ......................................................................................................47 Reserved -- Index 5Ch (Bank 0) ......................................................................................................47 VBAT Monitor Control Register -- Index 5Dh (Bank 0) ....................................................................47 Reserved Register --5Eh (Bank 0)...................................................................................................48 Reserved Register --5Fh (Bank 0) ...................................................................................................48 CPUTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 1)..................48 CPUTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 1) ..................48 CPUTIN Temperature Sensor Configuration Register - Index 52h (Bank 1)....................................49 CPUTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 1) .....................49 CPUTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 1) ......................50 CPUTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank1)...........50 CPUTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank 1)...........51 AUXTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 2)..................51 AUXTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 2)...................52 AUXTIN Temperature Sensor Configuration Register - Index 52h (Bank 2)....................................52 AUXTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 2)......................53 AUXTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 2) ......................53 AUXTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank 2) ..........53 AUXTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank 2)...........54
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
5.8.43 5.8.44 5.8.45 5.8.46 5.8.47 5.8.48 5.8.49 5.8.50 5.8.51 5.8.52 5.8.53 5.8.54 5.8.55 5.8.56 5.8.57 5.8.58 5.8.59 5.8.60 5.8.61 5.8.62 5.8.63 5.8.64 5.8.65 5.8.66 5.8.67 5.8.68 5.8.69 5.8.70 5.8.71 5.8.72 5.8.73 5.8.74 5.8.75 5.8.76 5.8.77 5.8.78 5.8.79 5.8.80 5.8.81 5.8.82 5.8.83 5.8.84 5.8.85 Interrupt Status Register 3 -- Index 50h (BANK4)............................................................................54 SMI# Mask Register 3 -- Index 51h (BANK 4)...............................................................................55 Reserved Register -- Index 52h (Bank 4) ........................................................................................55 BEEP Control Register 3-- Index 53h (Bank 4)................................................................................55 SYSTIN Temperature Sensor Offset Register -- Index 54h (Bank 4)...............................................56 CPUTIN Temperature Sensor Offset Register -- Index 55h (Bank 4) ..............................................56 AUXTIN Temperature Sensor Offset Register -- Index 56h (Bank 4) ..............................................57 Reserved Register -- Index 57h--58h (Bank4) .................................................................................57 Real Time Hardware Status Register I -- Index 59h (Bank 4)..........................................................57 Real Time Hardware Status Register II -- Index 5Ah (Bank 4) ........................................................58 Real Time Hardware Status Register III -- Index 5Bh (Bank 4) .......................................................58 Reserved Register -- Index 5Ch (Bank 4)........................................................................................59 Reserved Register -- Index 5Dh (Bank 4)........................................................................................59 Value RAM 2 Index 50h - 5Ah (BANK 5)......................................................................................59 Winbond Test Register -- Index 50h (Bank 6)..................................................................................60 Reserved Register--Index00h (Bank 0) ...........................................................................................60 SYSFANOUT Output Value Control Register-- 01h (Bank 0) ..........................................................60 Reserved Register--Index02h (Bank 0) ..........................................................................................61 CPUFANOUT Output Value Control Register-- 03h (Bank 0)..........................................................61 FAN Configuration Register I -- Index 04h (Bank 0) ........................................................................61 SYSTIN Target Temperature Register/ SYSFANIN Target Speed Register -- Index 05h (Bank 0) .62 CPUTIN Target Temperature Register/ CPUFANIN Target Speed Register -- Index 06h (Bank 0) 62 Tolerance of Target Temperature or Target Speed Register -- Index 07h (Bank 0) ........................63 SYSFANOUT Stop Value Register -- Index 08h (Bank 0) ...............................................................64 CPUFANOUT Stop Value Register -- 09h (Bank 0).........................................................................64 SYSFANOUT Start-up Value Register -- Index 0Ah (Bank 0) .......................................................65 CPUFANOUT Start-up Value Register -- Index 0Bh (Bank 0) .........................................................65 SYSFANOUT Stop Time Register -- Index 0Ch (Bank 0) ................................................................66 CPUFANOUT Stop Time Register -- Index 0Dh (Bank 0)................................................................66 Fan Output Step Down Time Register -- Index 0Eh (Bank 0) ..........................................................66 Fan Output Step Up Time Register -- Index 0Fh (Bank 0)...............................................................67 Reserved Register--Index10h (Bank 0) ..........................................................................................67 AUXFANOUT Output Value Control Register-- 11h (Bank 0) ..........................................................67 FAN Configuration Register II -- Index 12h (Bank 0) .......................................................................68 AUXTIN Target Temperature Register/ AUXFANIN Target Speed Register -- Index 13h (Bank 0) .68 Tolerance of Target Temperature or Target Speed Register -- Index 14h (Bank 0) ........................69 AUXFANOUT Stop Value Register -- Index 15h (Bank 0) ...............................................................69 AUXFANOUT Start-up Value Register -- Index 16h (Bank 0)..........................................................70 AUXFANOUT Stop Time Register -- Index 17h (Bank 0) ................................................................70 VRM & OVT Configuration Register -- Index 18h (Bank 0)..............................................................71 Reserved -- Index 19h (Bank 0).......................................................................................................72 User Defined Register -- Index 1A- 1Bh (Bank 0) ............................................................................72 Reserved Register-- Index 1Ch-1Fh (Bank 0) .................................................................................72
6. PLUG AND PLAY CONFIGURATION ............................................................................................. 73
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W83627THF/W83627THG
6.1 Compatible PnP ..................................................................................................................... 73
6.1.1 Extended Function Registers...........................................................................................................73 6.1.2 Extended Functions Enable Registers (EFERs) ..............................................................................74 6.1.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs) .............74
6.2
Configuration Sequence ........................................................................................................ 74
6.2.1 6.2.2 6.2.3 6.2.4 Enter the extended function mode ...................................................................................................74 Configuration the configuration registers .........................................................................................74 Exit the extended function mode .....................................................................................................75 Software programming example ......................................................................................................75
7. CONFIGURATION REGISTER........................................................................................................ 76 7.1 Chip (Global) Control Register............................................................................................... 76
7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7 7.1.8 Logical Device 0 (FDC)....................................................................................................................81 Logical Device 1 (Parallel Port) .......................................................................................................85 Logical Device 2 (UART A)..............................................................................................................86 Logical Device 3 (UART B)..............................................................................................................87 Logical Device 5 (KBC)....................................................................................................................89 Logical Device 7 (Game Port and MIDI Port and GPIO Port 1 and 5) .............................................90 Logical Device 8 (GPIO Port 2 This power of the Port is VCC source)............................................91 Logical Device 9 (GPIO Port 3, 4. These two ports are powered by VSB) ......................................93
7.2 7.3 8.1 8.2 9.1 9.2 9.3
Logical Device A (ACPI) ........................................................................................................ 94 Logical Device B (Hardware Monitor) .................................................................................. 101 Absolute Maximum Ratings ................................................................................................. 102 DC CHARACTERISTICS..................................................................................................... 102 Parallel Port Extension FDD ................................................................................................ 107 Parallel Port Extension 2FDD .............................................................................................. 108 Four FDD Mode ................................................................................................................... 108
8. AC/DC SPECIFICATIONS ............................................................................................................. 102
9. APPLICATION CIRCUITS.............................................................................................................. 107
10.HOW TO READ THE TOP MARKING ........................................................................................... 109 11.PACKAGE DIMENSIONS .............................................................................................................. 110 12.APPENDIX A : DEMO CIRCUIT .................................................................................................... 111 13.W83627THF VERSION CHANGE NOTICE 1................................................................................ 118 14.W83627THF APPLICATION NOTICE 4 (FOR E VERSION) ...................................................... 119 14.1 SYSFANOUT PWM Output Frequency Configuration Register - Index 00h ....................... 121 14.2 SYSFANOUT Output Value Select Register - Index 01h .................................................... 122 14.3 CPUFANOUT PWM Output Frequency Configuration Register - Index 02h....................... 123 14.4 CPUFANOUT Output Value Select Register - Index 03h .................................................... 124 14.5 FAN Configuration Register I - Index 04h ............................................................................ 125 14.6 SYSFANOUT Stop Value Register - Index 08h................................................................... 125 Publication Release Date: September 26, 2006 Revision 1.2
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W83627THF/W83627THG
14.7 CPUFANOUT Stop Value Register - Index 09h .................................................................. 126 14.8 SYSFANOUT Start-up Value Register - Index 0Ah ............................................................. 127 14.9 CPUFANOUT Start-up Value Register - Index 0Bh............................................................. 127 14.10 SYSFANOUT Stop Time Register - Index 0Ch ................................................................... 128 14.11 CPUFANOUT Stop Time Register - Index 0Dh ................................................................... 128 14.12 Fan Output Step Down Time Register - Index 0Eh ............................................................. 129 14.13 Fan Output Step Up Time Register - Index 0Fh .................................................................. 129 14.14 AUXFANOUT PWM Output Frequency Configuration Register - Index 10h ....................... 130 14.15 AUXFANOUT Output Value Select Register - Index 11h .................................................... 131 14.16 FAN Configuration Register II - Index 12h ........................................................................... 132 14.17 AUXFANOUT Stop Value Register - Index 15h................................................................... 133 14.18 AUXFANOUT Start-up Value Register - Index 16h ............................................................. 133 14.19 AUXFANOUT Stop Time Register - Index 17h.................................................................... 134
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W83627THF/W83627THG
1. GENERAL DESCRIPTION
W83627THF is a Winbond LPC I/O product. It integrates the following major peripheral functions in a chip: the disk driver adapter (FDC), Serial port (UART), Parallel port (SPP/EPP/ECP), Keyboard controller (KBC), SIR, Game port, MIDI port, Hardware Monitor, ACPI, On Now Wake-Up features. The disk drive adapter functions of W83627THF include a floppy disk drive controller compatible with the industry standard 82077/765, data separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide range of functions integrated onto the W83627THF greatly reduces the number of components required for interfacing with floppy disk drives. The W83627THF supports four 360K, 720K, 1.2M, 1.44M, or 2.88M disk drives and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s, 1 Mb/s, and 2 Mb/s. The W83627THF provides two high-speed serial communication ports (UARTs), one of which supports serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability, and a processor interrupts system. Both UARTs provide legacy speed with baud rate up to 115.2k bps and also advanced speed with baud rates of 230k, 460k, or 921k bps, which support higher speed modems. In addition, the W83627THF provides IR functions: IrDA 1.0 (SIR for 1.152K bps) The W83627THF supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP) and also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer port interface pins, also available are: Extension FDD Mode and Extension 2FDD Mode allowing one or two external floppy disk drives to be connected. The configuration registers support mode selection, function enable/disable, and power down function selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature TM demand of Windows 95/98 , which makes system resource allocation more efficient than ever. The W83627THF provides functions that complies with ACPI (Advanced Configuration and Power Interface), which includes support of legacy and ACPI power management through PME# or PSOUT# function pins. For OnNow keyboard Wake-Up, OnNow mouse Wake-Up. The W83627THF also has auto power management to reduce the power consumption. The keyboard controller is based on 8042 compatible instruction set with a 2K Byte programmable ROM and a 256-Byte RAM bank. Keyboard BIOS firmware are available with optional AMIKEY Phoenix MultiKey/42
TM TM -2,
, or customer code.
The W83627THF provides a set of flexible I/O control functions to the system designer through a set of General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured to provide a predefined alternate function.
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
The W83627THF is made to fully comply with Microsoft PC98 and PC99 Hardware Design Guide. Moreover, W83627THF is made to meet the specification of PC2001's requirement in the power management: ACPI 1.0/1.0b/2.0 and DPM (Device Power Management). The W83627THF contains a game port and a MIDI port. The game port is designed to support 2 joysticks and can be applied to all standard PC game control devices. They are very important for an entertainment or consumer computer. The W83627THF supports hardware status monitoring for personal computers. It can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stably and properly. Moreover, W83627THF support the Smart Fan control system, including the "Thermal TM TM Cruise " and "Speed Cruise " functions. Smart Fan can make system more stable and user friendly. The special characteristic of Super I/O product line is to avoid power rails short. This is especially true to a multi-power system where power partition is much more complex than a single-power one. Special care might be applied during layout stage or the IC will fail even though its intended function is OK.
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W83627THF/W83627THG
2. FEATURES
General
Meet LPC Spec. 1.1 Support LDRQ#(LPC DMA), SERIRQ (serial IRQ) Compliant with Microsoft PC98/PC2001 Hardware Design Guide Support DPM (Device Power Management), ACPI Programmable configuration settings Single 24 or 48 MHz clock input
FDC
Compatible with IBM PC AT disk drive systems Variable write pre-compensation with track selectable capability Support vertical recording format DMA enable logic 16-byte data FIFOs Support floppy disk drives and tape drives Detects all overrun and underrun conditions Built-in address mark detection circuit to simplify the read electronics FDD anti-virus functions with software write protect and FDD write enable signal (write data signal was forced to be inactive) Support up to four 3.5-inch or 5.25-inch floppy disk drives Completely compatible with industry standard 82077 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate Support 3-mode FDD, and its Win95/98/NT/2K/XP driver
UART
Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs MIDI compatible Fully programmable serial-interface characteristics: --- 5, 6, 7 or 8-bit characters --- Even, odd or no parity bit generation/detection --- 1, 1.5 or 2 stop bits generation
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
Internal diagnostic capabilities: --- Loop-back controls for communications link fault isolation --- Break, parity, overrun, framing error simulation Programmable baud generator allows division of 1.8461 MHz and 24 MHz by 1 to (216-1) Maximum baud rate up to 921k bps for 14.769 MHz and 1.5M bps for 24 MHz
Infrared
Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps
Parallel Port
Compatible with IBM parallel port Support PS/2 compatible bi-directional parallel port Support Enhanced Parallel Port (EPP) - Compatible with IEEE 1284 specification Support Extended Capabilities Port (ECP) - Compatible with IEEE 1284 specification Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A and B through parallel port Enhanced printer port back-drive current protection
Keyboard Controller
Asynchronous Access to Two Data Registers and One status Register Software compatibility with the 8042 Support PS/2 mouse Support port 92 Support both interrupt and polling modes Fast Gate A20 and Hardware Keyboard Reset 8 Bit Timer/ Counter Support binary and BCD arithmetic 6 MHz, 8 MHz, 12 MHz, or 16 MHz operating frequency
Game Port
Support two separate Joysticks Support every Joystick two axis (X, Y) and two button (A, B) controllers
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W83627THF/W83627THG
MIDI Port
The baud rate is 31.25 K baud rate 16-byte input FIFO 16-byte output FIFO
General Purpose I/O Ports
6 sets programmable general purpose I/O ports General purpose I/O ports can serve as simple I/O ports, interrupt steering inputs, watching dog timer output, power LED output, infrared I/O pins, KBC control I/O pins, suspend LED output, RSMRST# signal, PWROK signal, STR (suspend to DRAM) function, VID control function,
OnNow Functions
Keyboard Wake-Up by programmable keys Mouse Wake-Up by programmable buttons On Now Wake-Up from all of the ACPI sleeping states (S1-S5)
Hardware Monitor Functions
Smart fan control system, support "Thermal CruiseTM" and "Speed CruiseTM" 3 thermal inputs from optionally remote thermistors or 2N3904 transistors or PentiumTM II/III/4 thermal diode output 4 external voltage detect inputs. 3 intrinsic voltage monitoring (typical for Vbat, +5VSB , +5VCC) 3 fan speed monitoring inputs 3 fan speed control (DC analog output) Build in Case open detection circuit WATCHDOG comparison of all monitored values Programmable hysteresis and setting points for all monitored items Over temperature indicate output Issue SMI#, IRQ, OVT# to activate system protection Winbond Hardware DoctorTM Support Intel LDCMTM compatible
Package
128-pin PQFP
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
BLOCK DIAGRAM FOR 627THF
LRESET#, LCLK, LFRAME#, LAD[3:0], LDRQ#, SERIRQ
LPC Interface
Joystick interface signals MSI MSO General-purpose I/O pins Hardware monitor channel and Vref Keyboard/Mouse data and clock
Game Port MIDI
FDC
Floppy drive interface signals Serial port A, B interface signals IRRX IRTX
URA, B
GPIO
IR
HM
PRT
Printer port interface signals
KBC
ACPI
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W83627THF/W83627THG
PIN CONFIGURATION FOR 627THF
Note: Please refer to Section 8.2 DC CHARACTERISTICS for details.
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
3. PIN DESCRIPTION
TYPE DESCRIPTION
I/O8t I/O12t I/O24t I/O12tp3 I/O12ts I/O24ts I/O24tsp3 I/OD12t I/OD24t I/OD12ts I/OD16ts I/OD24ts I/OD12cs I/OD16cs
I/OD12csd
TTL level bi-directional pin with 8mA source-sink capability TTL level bi-directional pin with 12mA source-sink capability TTL level bi-directional pin with 24 mA source-sink capability 3.3V TTL level bi-directional pin with 12mA source-sink capability TTL level Schmitt-trigger bi-directional pin with 12mA source-sink capability TTL level Schmitt-trigger bi-directional pin with 24mA source-sink capability 3.3V TTL level Schmitt-trigger bi-directional pin with 24mA source-sink capability TTL level bi-directional pin and open-drain output with 12mA sink capability TTL level bi-directional pin and open-drain output with 24mA sink capability TTL level Schmitt-trigger bi-directional pin and open-drain output with 12mA sink capability TTL level Schmitt-trigger bi-directional pin and open-drain output with 16mA sink capability TTL level Schmitt-trigger bi-directional pin and open-drain output with 24mA sink capability CMOS level Schmitt-trigger bi-directional pin and open-drain output with 12mA sink capability CMOS level Schmitt-trigger bi-directional pin and open-drain output with 16mA sink capability CMOS level Schmitt-trigger bi-directional pin with internal pull down resistor and opendrain output with 12mA sink capability CMOS level Schmitt-trigger bi-directional pin with internal pull up resistor and open-drain output with 12mA sink capability Output pin with 4 mA source-sink capability Output pin with 8 mA source-sink capability Output pin with 12 mA source-sink capability Output pin with 16 mA source-sink capability Output pin with 24 mA source-sink capability 3.3V output pin with 12 mA source-sink capability 3.3V output pin with 24 mA source-sink capability Open-drain output pin with 12 mA sink capability Open-drain output pin with 24 mA sink capability
I/OD12csu O4 O8 O12 O16 O24 O12p3 O24p3 OD12 OD24
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W83627THF/W83627THG
PIN DESCRIPTION, continued.
TYPE
DESCRIPTION
OD12p3 INt INtp3 INtd INtu INts INtsp3 INc INcd INcs INcsu AOUT AIN
3.3V open-drain output pin with 12 mA sink capability TTL level input pin 3.3V TTL level input pin TTL level input pin with internal pull down resistor TTL level input pin with internal pull up resistor TTL level Schmitt-trigger input pin 3.3V TTL level Schmitt-trigger input pin CMOS level input pin CMOS level input pin with internal pull down resistor CMOS level Schmitt-trigger input pin CMOS level Schmitt-trigger input pin with internal pull up resistor Analog output Analog input
3.1
LPC Interface
PIN I/O FUNCTION
SYMBOL
CLKIN PME# PCICLK LDRQ# SERIRQ LAD[3:0] LFRAME# LRESET#
18 19 21 22 23 24-27 29 30
INt OD8 INtsp3 OUT12tp3 I/OD12tp3 I/O12tp3 INtsp3 INtsp3
System clock input. According to the input frequency 24MHz or 48MHz, it is selectable through register. Default is 24MHz input. erated P PCI 33 MHz clock input. Encoded DMA Request signal. Serial IRQ input/Output. These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral. Indicates start of a new cycle or termination of a broken cycle. Reset signal. It can connect to PCIRST# signal on the host.
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
3.2 FDC Interface
PIN I/O FUNCTION
SYMBOL
DRVDEN0
1
OD24
Drive Density Select bit 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). Motor A On. When set to 0, this pin enables disk drive 0. This is an open drain output. Drive Select A. When set to 0, this pin enables disk drive A. This is an open drain output. Direction of the head step motor. An open drain output. Logic 1 = outward motion Logic 0 = inward motion Step output pulses. This active low open drain output produces a pulse to move the head to another track. Write data. This logic low open drain writes pre-compensation serial data to the selected FDD. An open drain output. Write enable. An open drain output. Track 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the outermost track. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). Write protected. This active low Schmitt input from the disk drive indicates that the diskette is write-protected. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). The read data input signal from the FDD. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). Head select. This open drain output determines which disk drive head is active.
INDEX#
3
INcs
MOA# DSA#
4 6
OD24 OD24
DIR#
8
OD24
STEP# WD# WE#
9 10 11
OD24 OD24 OD24 INcs
TRAK0#
13
WP#
14
INcs
RDATA#
15
INcs
HEAD#
16
OD24
Logic 1 = side 0 Logic 0 = side 1 Diskette change. This signal is active low at power on and whenever the diskette is removed. This input pin is pulled up internally by a 1 K . The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN).
DSKCHG#
17
INcs
- 10 -
W83627THF/W83627THG
3.3 Multi-Mode Parallel Port
PIN I/O FUNCTION
The following pins have alternate functions, which are controlled by CR28 and L3-CRF0.
SYMBOL
PRINTER MODE: SLCT 31 INt An active high input on this pin indicates that the printer is selected. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. PRINTER MODE: PE 32 INt An active high input on this pin indicates that the printer has detected the end of the paper. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: BUSY 33 INt An active high input indicates that the printer is not ready to receive data. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. PRINTER MODE: ACK# ACK# 34 INt An active low input on this pin indicates that the printer has received data and is ready to accept more data. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: ERR# ERR# 45 INt An active low input on this pin indicates that the printer has encountered an error condition. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: SLIN# SLIN# 43 OD12 Output line for detection of printer selection. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: INIT# INIT# 44 OD12 Output line for the printer initialization. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: AFD# AFD# 46 OD12 An active low output from this pin causes the printer to auto feed a line after a line is printed. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
Multi-Mode Parallel Port, continued
SYMBOL
PIN
I/O
FUNCTION
PRINTER MODE: STB# STB# 47 OD12 An active low output is used to latch the parallel data into the printer. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: PD0 PD0 42 I/O12t Parallel port data bus bit 0. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: PD1 PD1 41 I/O12t Parallel port data bus bit 1. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: PD2 PD2 40 I/O12t Parallel port data bus bit 2. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: WP2# PRINTER MODE: PD3 PD3 39 I/O12t Parallel port data bus bit 3. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: PD4 PD4 38 I/O12t Parallel port data bus bit 4. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: PD5 PD5 37 I/O12t Parallel port data bus bit 5. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: PD6 PD6 36 I/O12t Parallel port data bus bit 6. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: PD7 PD7 35 I/O12t Parallel port data bus bit 7. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.
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W83627THF/W83627THG
3.4 Serial Port Interface
PIN I/O FUNCTION
SYMBOL
CTSA#
49
INt INt I/O12t INt
CTSB#
78
DSRA#
50
DSRB#
79
INt
RTSA# HEFRAS
51
I/O8t
RTSB#
80
I/O8t
DTRA# PNPCSV#
52
I/O8t
DTRB# SINA SINB
81 53 82
I/O8t INt INtt
SOUTA PENKBC
54
I/O8t
Clear To Send. It is the modem control input. The function of these pins can be tested by reading bit 4 of the handshake status register. Clear To Send. It is the modem control input. The function of these pins can be tested by reading bit 4 of the handshake status register. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. UART A Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. During power-on reset, this pin is pulled down internally and is defined as HEFRAS, which provides the power-on value for CR26 bit 6 (HEFRAS). A 4.7 k is recommended if intends to pull up. (select 4EH as configuration I/O ports address) UART B Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. UART A Data Terminal Ready. An active low signal informs the modem or data set that the controller is ready to communicate. During power-on reset, this pin is pulled down internally and is defined as PNPCSV#, which provides the power-on value for CR24 bit 0 (PNPCSV#). A 4.7 k is recommended if intends to pull up. (clear the default value of FDC, UARTs, PRT, Game port and MIDI port) UART B Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. Serial Input. It is used to receive serial data through the communication link. Serial Input. It is used to receive serial data through the communication link. UART A Serial Output. It is used to transmit serial data out to the communication link. During power-on reset, this pin is pulled down internally and is defined as PENKBC, which provides the power-on value for CR24 bit 2 (ENKBC). A 4.7 k resistor is recommended if intends to pull up. (enable KBC)
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
Serial Port Interface, continued
SYMBOL
PIN
I/O
FUNCTION
SOUTB PEN48 DCDA# DCDB# RIA# RIB#
83
I/O8t
56 84 57 85
INt INt INt INt
UART B Serial Output. During power-on reset, this pin is pulled down internally and is defined as PEN48, which provides the power-on value for CR24 bit 6 (EN48). A 4.7 k resistor is recommended if intends to pull up. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set.
3.5
KBC Interface
PIN I/O FUNCTION
SYMBOL
GA20M KBRST KDAT MCLK MDAT
59 60 63 65 66
OUT12 OUT12 I/OD16cs I/OD16cs I/OD16cs
Gate A20 output. This pin is high after system reset. (KBC P21) Keyboard reset. This pin is high after system reset. (KBC P20) Keyboard Data. PS2 Mouse Clock. PS2 Mouse Data.
3.6
Hardware Monitor Interface
SYMBOL PIN I/O FUNCTION
BEEP CASEOPEN# VIN0 VIN1 VIN2 CPUVCORE VREF AUXTIN CPUTIN
58 76 99 98 97 100 101 102 103
OD8 INt AIN AIN AIN AIN AOUT AIN AIN
Beep function for hardware monitor. This pin is low after system reset. CASE OPEN. An active low input from an external device when case is opened. This signal can be latched if pin VBAT is connect to battery, even W83627THF is power off. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. Reference Voltage for temperature maturation. Temperature sensor 3 inputs. It is used for temperature maturation. Temperature sensor 2 inputs. It is used for CPU1 temperature maturation.
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W83627THF/W83627THG
Hardware Monitor Interface, continued.
SYMBOL
PIN
I/O
FUNCTION
SYSTIN OVT# AUXFANIN CPUFANIN SYSFANIN SYSFANOUT CPUFANOUT AUXFANOUT
104 111 5 112 113 116 115 7
AIN OD12 I/O12ts
Temperature sensor 1 input. It is used for system temperature maturation. Over temperature Shutdown Output. temperature is over temperature limit. 0V to +5V amplitude fan tachometer input. It indicated the
AOUT
Fan speed control. Output analog voltage level to control the Fan's speed.
3.7
Game Port
PIN 128 127 126 I/O INcs I/OD12cs INcs I/OD12cs I/OD12cs I/OD12cs I/OD12cs I/OD12cs 124 I/OD12cs 123 I/OD12cs I/OD12cs INcs I/OD12cs INcs I/OD12cs FUNCTION Active-low, Joystick I switch input 1. (Default) General purpose I/O port 1 bit 0. Active-low, Joystick II switch input 1. (Default) General purpose I/O port 1 bit 1. Joystick I timer pin. this pin connects to X positioning variable resistors for the Joystick. (Default) General purpose I/O port 1 bit 2. Joystick II timer pin. this pin connects to X positioning variable resistors for the Joystick. (Default) General purpose I/O port 1 bit 3. Joystick II timer pin. this pin connects to Y positioning variable resistors for the Joystick. (Default) General purpose I/O port 1 bit 4. Joystick I timer pin. this pin connects to Y positioning variable resistors for the Joystick. (Default) General purpose I/O port 1 bit 5. Active-low, Joystick II switch input 2. This pin has an internal pullup resistor. (Default) General purpose I/O port 1 bit 6. Active-low, Joystick I switch input 2. This pin has an internal pullup resistor. (Default) General purpose I/O port 1 bit 7.
SYMBOL GPSA1 GP10 GPSB1 GP11 GPX1 GP12 GPX2 GP13 GPY2 GP14 GPY1 GP15 GPSB2 GP16 GPSA2 GP17
125
122
121
3.8
3.8.1
General Purpose I/O Port
General Purpose I/O Port 1 (Power source is Vcc)
see 3.7 Game Port
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
3.8.2 General Purpose I/O Port 2 (Power source is Vcc)
PIN I/O FUNCTION
SYMBOL
GP20 MSO IRQIN0 GP21 MSI GP22 GP23 GP24 GP25 GP26 SMI# IRQIN1
I/OD12t 120 OUT12 INt I/OD12t INtu I/OD12t I/OD12t I/OD12t I/OD12t I/OD12t OD24 INt
General purpose I/O port 2 bit 0. MIDI serial data output. (Default) IRQ channel input 0. General purpose I/O port 2 bit 1. MIDI serial data input. It is internally pulled up by a 40 K ohms resistor. (Default) General purpose I/O port 2 bit 2. (Default) General purpose I/O port 2 bit 3. (Default) General purpose I/O port 2 bit 4. (Default) General purpose I/O port 2 bit 5. (Default) General purpose I/O port 2 bit 6. (Default) System Management Interrupt channel output. IRQ channel input 1.
119 118 96 95 94 93 2
3.8.3
General Purpose I/O Port 3, 4 (Power source is VSB)
PIN I/O FUNCTION
SYMBOL
GP30 GP31 GP32 PLED GP33 WDTO GP34 IRRX IRTX GP35 GP37 SUSLED/ GP40
92 91 90
I/OD12t I/OD12t I/OD24t OUT24 I/OD12t OUT12 I/OD12ts INts OUT12 I/OD12t I/OD24t OUT24 I/OD8t
General purpose I/O port 3 bit 0. General purpose I/O port 3 bit 1. General purpose I/O port 3 bit 2. Power LED output. General purpose I/O port 3 bit 3. (Default) Watchdog time out output. General purpose I/O port 3 bit 4. IRRX input. (Default)
89
88 87 86 64
Infrared Transmitter Output. (Default) General purpose I/O port 3 bit 5. (Default) General purpose I/O port 3 bit 7. Suspend LED output, it can program to flash when suspend state. This function can work without VCC. (Default) General purpose I/O port 4 bit 0. This pin must be connected with a pull high resistor to prevent into Winbond Test Mode.
75
- 16 -
W83627THF/W83627THG
General Purpose I/O Port 3, 4 (Power source is VSB), continued.
SYMBOL
PIN
I/O
FUNCTION
GP41 SLP_SX# GP42 PWRCTL# GP43 PWROK GP44 RSMRST# GP45 GP46 PSIN GP47 PSOUT#
73
I/OD12t INt I/OD12t OD12 I/OD12t OD12 I/OD12t OD12 I/OD12t I/OD12t INtd I/OD12t OD12
General purpose I/O port 4 bit 1. SLP_S3# input. (Default) General purpose I/O port 4 bit 2. This pin generates the PWRCTL# signal while the power failure. (Default) General purpose I/O port 4 bit 3. This pin generates the PWROK signal while the VCC come in. (Default) General purpose I/O port 4 bit 4. This pin generates the RSMRST signal while the VSB come in. (Default) General purpose I/O port 4 bit 5. General purpose I/O port 4 bit 6. Panel Switch Input. This pin is high active with an internal pull down resistor. (Default) General purpose I/O port 4 bit 7. Panel Switch Output. This signal is used for Wake-Up system from S5c o l d state. This pin is pulse output, active low. (Default)
72
71
70 69 68
67
3.8.4
General Purpose I/O Port 5 (Power source is VCC)
PIN I/O FUNCTION
SYMBOL
GP50 GP51 GP52 GP53 GP54 GP55
110 109 108 107 106 105
I/O12tp3 I/O12tp3 I/O12tp3 I/O12tp3 I/O12tp3 I/O12tp3
General purpose I/O port 5 bit 0. General purpose I/O port 5 bit 1. General purpose I/O port 5 bit 2. General purpose I/O port 5 bit 3. General purpose I/O port 5 bit 4. General purpose I/O port 5 bit 5.
Note. The GPIO Port 5 could be used as VID input / output function for VRD10.
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
3.9 POWER PINS
SYMBOL PIN FUNCTION
VCC 5VSB 3VCC AVCC VBAT AGND GND
12, 48 61 28 114 74 117 20, 55
+5V power supply for the digital circuitry. +5V stand-by power supply for the digital circuitry. +3.3V power supply for driving 3V on host interface. Analog VCC input. Internally supplier to all analog circuitry. Battery voltage input. Analog ground. Ground.
3.10
GPIO PIN Power Source
SYMBOL POWER SOURCE
GPIO port 1 GPIO port 2 GPIO port 3 GPIO port 4 GPIO port 5
Vcc Vcc VSB VSB Vcc
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W83627THF/W83627THG
4. GENERAL PURPOSE I/O
W83627THF provides 36 input/output ports that can be individually configured to perform a simple basic I/O function or a pre-defined alternate function. Those 36 GP I/O ports are divided into five groups . The first and fifth groups are configured through control registers in logical device 7, the second group in logical device 8, and the third and forth groups in logical device 9. Users can configure each individual port to be an input or output port by programming respective bit in selection register (CRF0/F3: 0 = output, 1 = input). Invert port value by setting inversion register (CRF2/F5: 0 = non-inverse, 1 = inverse). Port value is read/written through data register (CRF1/CRF4). Table 4-1 and 4-2 give more details on GPIO's assignment. Figure 4-1 shows the GP I/O port's structure. After power-on reset those ports default to perform basic input function which maintains its previous settings until a battery loss condition.
SELECTION BIT 0 = OUTPUT 1 = INPUT
INVERSION BIT 0 = NON INVERSE 1 = INVERSE BASIC I/O OPERATIONS
0 0 1 1
0 1 0 1 Table 4-1
Basic non-inverting output Basic inverting output Basic non-inverting input Basic inverting input
GP I/O PORT DATA REGISTER
REGISTER BIT ASSIGNMENT
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 BIT 2
GP I/O PORT
GP10 GP11 GP12 GP13 GP14 GP15 GP16 GP17 GP20 GP21 GP22 GP23 GP24 GP25 GP26
GP1(VCC POWER)
GP2(VCC POWER)
BIT 3 BIT 4 BIT 5 BIT 6
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
continued.
GP I/O PORT DATA REGISTER
REGISTER BIT ASSIGNMENT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5
GP I/O PORT GP30 GP31 GP32 GP33 GP34 GP35 GP36 GP37 GP40 GP41 GP42 GP43 GP44 GP45 GP46 GP47 GP50 GP51 GP52 GP53 GP54 GP55
GP3(VSB POWER)
GP4(VSB POWER)
GP5(VCC POWER)
Table 4-2
Figure 4-1
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W83627THF/W83627THG
5. HARDWARE MONITOR
5.1 General Description
The W83627THF can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stable and properly. W83627THF provides LPC interface to access hardware . An 8-bit analog-to-digital converter (ADC) was built inside W83627THF. The W83627THF can simultaneously monitor 3 analog voltage inputs (addition monitor VBAT, 5VSB & 5VCC power), 3 fan tachometer inputs, 3 remote temperature inputs and one case-open detection signal. The remote temperature sensing can be performed by thermistors, 2N3904 NPN-type transistors, or directly from IntelTM CPU thermal diode output. Also the W83627THF provides: 3 analog outputs for fan speed control. Beep tone output for warning; SMI#(can through SERIRQ pin), OVT# signals for system protection events. Through the application software or BIOS, the users can read all the monitored parameters of system from time to time. And a pop-up warning can be also activated when the monitored item was out of the proper/preset range. The application software could be Winbond's Hardware DoctorTM, or IntelTM LDCM (LanDesk Client Management), or other management application software. Also the users can set up the upper and lower limits (alarm thresholds) of these monitored parameters and to activate one programmable and maskable interrupts. An optional beep tone could be used as warning signal when the monitored parameters are out of the preset range.
5.2
Access Interface
W83627THF uses LPC Bus to access which the ports address of low byte (bit2~bit0) are defined in the port 5h and 6h. The other higher bits of these ports are set by W83627THF itself. The general decoded address is set to port 295h and port 296h. These two ports are described as following: Port 295h: Index port. Port 296h: Data port. The register structure is showed as the Figure 5-1
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
Smart Fan Configuration Registers 00h-1Fh
Configuration Register 40h Interrupt Status Registers 41h, 42h SMI# Mask Registers 43h-44h Fan Divisor Register I 47h
BANK 1 CPUTIN Temperature Control/Staus Registers 50h~56h BANK 2 AUXTIN Temperature Control/Staus Registers 50h~56h
BANK 4 Interrupt Status & SMI Mask Registers 50h~51h
LPC Bus Monitor Value Registers 20h~3Fh Port 5h Device ID 49h
BANK 4 Beep Control Registers 53h
Index Register
BANK 4 Temperature Offset Registers 54h~56h
Fan Divisor Register I 4Bh SMI#/OVT# Control Register 4Ch Fan IN/OUT and BEEP Control Register 4Dh Port 6h Data Register Bank Select for 50h~5Fh Registers. 4Eh Winbond Vendor ID 4Fh BANK 0 Winbond Test Registers 50h~55h BANK 0 BEEP Control Registers 56h~57h BANK 0 Chip ID Register 58h
BANK 4 Read Time Status Registers 59h~5Bh
BANK 5 Monitor Value Registers 59h~5Bh
BANK 0 Temperature Sensor Type Configuration & Fan Divisor Bit2 Registers 59h,5Dh
Figure 5-1 : LPC interface access diagram
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W83627THF/W83627THG
5.3 Analog Inputs
The maximum input voltage of the analog pin is 4.096V because the 8-bit ADC has a 16mv LSB. Really, the application of the PC monitoring would most often be connected to power suppliers. The CPU Vcore voltage, +3.3V, battery(pin 74), AVCC(pin 114) and 5VSB voltage can directly connected to these analog inputs. The +12V voltage inputs should be reduced a factor with external resistors so as to obtain the input range. As Figure 3.2 shows.
AVCC Power Inputs VBAT 5VSB
Pin 114 Pin 74 Pin 61
VIN1(+3.3V) CPUVCORE R1 V1 Positive Voltage Input R2 VIN0
Pin 98 Pin 100 Pin 99 8-bit ADC with 16mV LSB
Negative Voltage Input
V2 R5
R3
VIN2
Pin 97
R4 RTHM 10K@25 C, beta=3435K R 10K, 1% VREF R 30K, 1% AUXTIN CPUTIN SYSTIN CPUD+ CAP,3300p CPUDPin 102 Pin 103 Pin 104 Pin 101
Figure. 5-2
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
5.3.1 Monitor over 4.096V voltage:
The +12V input voltage can be expressed as following equation.
VIN 0 = V1 x
R2 R1 + R2
The value of R1 and R2 can be selected to 28K Ohms and 10K Ohms, respectively, when the input voltage V1 is 12V. The node voltage of VIN0 can be subject to less than 4.096V for the maximum input range of the 8-bit ADC. The -12V input voltage can be expressed as following equation.
VIN 2 = (V2 - 3.6) x
R4 + 3.6, whereV2 = -12 R3 + R 4
The value of R3 and R4 can be selected to 232K Ohms and 56K Ohms, respectively, when the input voltage V2 is -12V. The node voltage of VIN2 can be subject to less than 4.096V for the maximum input range of the 8-bit ADC. The Pin 114 is connected to the power supply VCC with +5V. There are two functions in this pin with 5V. The first function is to supply internal analog power in the W83627THF and the second function is that this voltage with 5V is connected to internal serial resistors to monitor the +5V voltage. The W83627THF internal two serial resistors are 34K ohms and 51K ohms so that input voltage to ADC is 3V which is less than 4.096V of ADC maximum input voltage. The express equation can represent as follows.
Vin = VCC x
51K 3V 51K + 34 K
where VCC is set to 5V. The Pin 61 is connected to 5VSB voltage. W83627THF monitors this voltage and the internal two serial resistors are 34K and 51K so that input voltage to ADC is 3V which less than 4.096V of ADC maximum input voltage.
5.3.2
CPUVCORE voltage detection method:
W83627THF provides two detection methods for CPUVCORE(pin100). (1). VRM8 method: The LSB of this mode is 16mV. This means that the detected voltage equals to the reading of this voltage register multiplies 16mV. The formula is as the following: Detected Voltage =
Re ading 0.016 V
(2). VRM9 method: (Default) The LSB of this mode is 4.88mV which is especially designed for the low voltage CPU. The formula is as the following: Detected Voltage = Re ading 0.00488 + 0.69 V
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W83627THF/W83627THG
5.3.3 Temperature Measurement Machine
The temperature data format is 8-bit two's-complement for sensor SYSTIN and 9-bit two'scomplement for sensor CPUTIN and AUXTIN. The 8-bit temperature data can be obtained by reading the CR[27h]. The 9-bit temperature data can be obtained by reading the 8 MSBs from the Bank1/Bank2 CR[50h] and the LSB from the Bank1/Bank2 CR[51h] bit 7. The format of the temperature data is show in Table 5-1.
TEMPERATURE
8-BIT DIGITAL OUTPUT
9-BIT DIGITAL OUTPUT
8-Bit Binary +125C +25C +1C +0.5C +0C -0.5C -1C -25C -55C 0111,1101 0001,1001 0000,0001 0000,0000 1111,1111 1110,0111 1100,1001
8-Bit Hex 7Dh 19h 01h 00h FFh E7h C9h Table 5-1
9-Bit Binary 0,1111,1010 0,0011,0010 0,0000,0010 0,0000,0001 0,0000,0000 1,1111,1111 1,1111,1110 1,1100,1110 1,1001,0010
9-Bit Hex 0FAh 032h 002h 001h 000h 1FFh 1FFh 1CEh 192h
5.3.3.1
Monitor temperature from thermistor:
The W83627THF can connect three thermistors to measure three different environment temperature. The specification of thermistor should be considered to (1) value is 3435K, (2) resistor value is 10K ohms at 25C. In the Figure 5-2, the themistor is connected by a serial resistor with 10K Ohms, then connect to VREF (Pin 101). 5.3.3.2 Monitor temperature from Pentium IITM/Pentium IIITM thermal diode or bipolar transistor 2N3904 The W83627THF can alternate the thermistor to Pentium IITM/Pentium IIITM thermal diode interface or transistor 2N3904 and the circuit connection is shown as Figure 5-3. The pin of Pentium IITM/Pentium IIITM D- is connected to AGND and the pin D+ is connected to temperature sensor pin in the W83627THF. The resistor R=30K ohms should be connected to VREF to supply the diode bias current and the bypass capacitor C=3300pF should be added to filter the high frequency noise. The transistor 2N3904 should be connected to a form with a diode, that is, the Base (B) and Collector (C) in the 2N3904 should be tied together to act as a thermal diode.
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
VREF R=30K,1%
Bipolar Transistor Temperature Sensor
VTIN R=30K,1% C=3300pF C B E 2N3904
W83627THF
OR
Pentium II/III CPU Therminal Diode D+ C=3300pF DAGND
CPUTIN
Figure 5-3
5.4
5.4.1
FAN Speed Count and FAN Speed Control
Fan speed count
Inputs are provides for signals from fans equipped with tachometer outputs. The level of these signals should be set to TTL level, and maximum input voltage can't be over VCC. If the input signals from the tachometer outputs are over the VCC, the external trimming circuit should be added to reduce the voltage to obtain the input specification. The normal circuit and trimming circuits are shown as Figure 5-4 ~ 5-7. Determine the fan counter according to:
1.35 x 10 6 Count = RPM x Divisor
In other words, the fan speed counter has been read from register CR28 or CR29 or CR2A, the fan speed can be evaluated by the following equation.
RPM =
1.35 x 10 6 Count x Divisor
The default divisor is 2 and defined at CR47.bit7~4, CR4B.bit7~6, and Bank0 CR5D.bit5~7 which are three bits for divisor. That provides very low speed fan counter such as power supply fan. The followed table is an example for the relation of divisor, RPM, and count
- 26 -
W83627THF/W83627THG
DIVISOR
NOMINAL RPM
TIME PER REVOLUTION
COUNTS
70% RPM
TIME FOR 70%
1 2 (default) 4 8 16 32 64 128
8800 4400 2200 1100 550 275 137 68
6.82 ms 13.64 ms 27.27 ms 54.54 ms 109.08 ms 218.16 ms 436.32 ms 872.64 ms Table 5-2
153 153 153 153 153 153 153 153
6160 3080 1540 770 385 192 96 48
9.84 ms 19.48 ms 38.96 ms 77.92 ms 155.84 ms 311.68 ms 623.36 ms 1246.72 ms
+12V
+5V
+12V
Pull-up resister 4.7K Ohms
Pull-up resister 4.7K Ohms
+12V Pin112 -113,5 FAN Out GND Fan Input
+12V 14K~39K FAN Out GND Pin 112-113,5 Fan Input
W83627THFD
FAN Connector FAN Connector
10K
W83627THFD
Figure 5-4. Fan with Tach Pull-Up to +5V
Figure 5-5. Fan with Tach Pull-Up to +12V, or Totem-Pole Output and Register Attenuator
+12V
+12V
Pull-up resister > 1K +12V FAN Out GND Fan Input Pin 112-113,5 +12V
Pull-up resister < 1K or totem-pole output > 1K FAN Out Fan Input Pin 112-113,5
3.9V Zener
W83627THFD
GND 3.9V Zener
W83627THFD
FAN Connector
FAN Connector Figure 5-7. Fan with Tach Pull-Up to +12V, or Totem-Pole Putput and Zener Clamp
Figure 5-6. Fan with Tach Pull-Up to +12V and Zener Clamp
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W83627THF/W83627THG
5.4.2 Fan speed control
The W83627THF has a 4 bit DAC which produces 0 to 5 volts DC output that provides maximum 3 sets for fan speed control. The analog output can be programmed in the Bank0 Index 01h, Index 03h and Index 11h. The default value is 0xFY,Y is reserved nibble, that is default output value is 5 V. The expression of output voltage can be represented as follow ,
OUTPUT Voltage = AVCC x
Programmed 4 - bit Register Value 16
The application circuit is shown as follow,
IO+12V
IO+12V
Q1
NPN
R1
FANOUT 0
4 3 +
LM358 1
C1
0.1U
2
-
Tachometer output
11 IO-12V
R3
FAN 28K
3 2 1
R4
20K
Figure 5-8 Must be take care when choosing the OP-AMP and the transistor. The OP-AMP is used for amplify the 5V range of the DC output up to 12V . The transistor should has a suitable value to avoid its base current pulling down the OP-AMP 's output and gain the common current to operate the fan at fully speed.
5.5
SmartFanTM Control
SmartFanTM Control provides two mechanisms. One is Thermal Cruise mode and the other is Fan Speed Cruise mode. No matter which mode you use, the FAN will full speed run at beginning.
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W83627THF/W83627THG
5.5.1 Thermal Cruise mode
There are maximum 3 pairs of Temperature/FANOUT control at this mode: SYSTIN with SYSFANOUT, CPUTIN with CPUFANOUT, AUXTIN with AUXFANOUT. At this mode, W83627THF provides the Smart Fan system which can control the fan speed automatically depend on current temperature to keep it with in a specific range. At first a wanted temperature and interval must be set (ex. 55 C 3 C) by BIOS, as long as the real temperature remains below the setting value, the fan will be off. Once the temperature exceeds the setting high limit temperature ( 58C), the fan will be turned on with a specific speed set by BIOS (ex: 3.75 V) and automatically controlled its DC voltage output with the temperature varying. Three conditions may occur : (1) If the temperature still exceeds the high limit (ex: 58C), DC Fan output voltage will increase slowly. If the fan has been operating in its fully speed but the temperature still exceeds the high limit(ex: 58C) after 3 minutes, a warning message will be issued to protect the system. (2) If the temperature goes below the high limit (ex: 58C), but above the low limit (ex: 52C), the fan speed will be fixed at the current speed because the temperature is in the target area(ex: 52 C ~ 58C). (3) If the temperature goes below the low limit (ex: 52C), DC Fan output voltage will decrease slowly to 0 until the temperature exceeds the low limit. Figure 5-9 and 5-10 give the illustration for Thermal Cruise Mode .
A Tolerance Target Temperature Tolerance 52C 58C 55C
B
C
D
DC Output Voltage
5 2.5 0
Fan Start = 1.875 V
Figure 5-9
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
A Tolerance Target Temperature Tolerance 52C DC Output Voltage 58C 55C
B
C
D
5 2.5 0
Fan Start = 1.875V Fan Start = 1.875V Fan Stop = 1.25V
Figure 5-10 One more protection is provided that DC FAN output voltage will not be decreased to 0 in the above (3) situation in order to keep the fans running with a minimum speed. By setting CR[12h] bit3-5 to 1, FAN output voltage will be decreased to the " Stop Value " which are defined at CR[08h],CR[09h] and CR[15h].
5.5.2
Fan Speed Cruise mode
There are 3 pairs of FANIN/FANOUT control at this mode: SYSFANIN with SYSFANOUT, CPUFANIN with CPUFANOUT, AUXFANIN with AUXFANOUT. At this mode, W83627THF provides the Smart Fan system which can control the fan speed automatically depend on current fan speeds to keep it with in a specific range. A wanted fan speed count and interval must be set (ex. 160 10 ) by BIOS. As long as the fan speed count is the specific range, output voltage will keep the current value. If current fan speed count is higher than the high limit (ex. 160+10), output voltage will be increased to keep the count less than the high limit. Otherwise, if current fan speed is less than the low limit(ex. 160-10), output voltage will be decreased to keep the count higher than the low limit. See Figure 5-11 example.
Count 170 160 150 A C
DC Output Voltage
5 2.5 0
Figure 5-11
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W83627THF/W83627THG
5.5.3 Manual Control Mode
Smart Fan control system can be disabled and the fan speed control algorithmic can be programmed by BIOS or application software. The programming method is just as section 5.4.2.
5.6
SMI# interrupt mode
The SMI#/IRQIN1 pin(pin2) is a multi-function pin. The SMI# function is selected at Configuration Register CR[2Ah] bit 2.
5.6.1
Voltage SMI# mode :
SMI# interrupt for voltage is Two-Times Interrupt Mode. Voltage exceeding high limit or going below low limit will causes an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. (Figure 5-12 )
5.6.2
Fan SMI# mode :
SMI# interrupt for fan is Two-Times Interrupt Mode. Fan count exceeding the limit, or exceeding and then going below the limit, will causes an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. (Figure 5-13 )
High limit
Low limit
Fan Count limit
SMI#
*
*
*
*
SMI#
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 5-12
Figure 5-13
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
5.6.3 The W83627THF temperature sensor 1(SYSTIN) SMI# interrupt has 3 modes:
(1) Comparator Interrupt Mode
Setting the THYST (Temperature Hysteresis) limit to 127C will set temperature sensor 1 SMI# to the Comparator Interrupt Mode. Temperature exceeds TO (Over Temperature) Limit causes an interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the TO , the interrupt will occur again when the next conversion has completed. If an interrupt event has occurred by exceeding TO and not reset, the interrupts will not occur again. The interrupts will continue to occur in this manner until the temperature goes below TO. (Figure 5-14 ) . Setting the THYST lower than TO will set temperature sensor 1 SMI# to the Interrupt Mode. The following are two kinds of interrupt modes, which are selected by Index 4Ch bit5 :
(2) Two-Times Interrupt Mode
Temperature exceeding TO causes an interrupt and then temperature going below THYST will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. Once an interrupt event has occurred by exceeding TO , then reset, if the temperature remains above the THYST , the interrupt will not occur. (Figure 5-15 )
(3) One-Time Interrupt Mode
Temperature exceeding TO causes an interrupt and then temperature going below THYST will not cause an interrupt. Once an interrupt event has occurred by exceeding TO , then going below THYST, an interrupt will not occur again until the temperature exceeding TO. (Figure 5-16 )
T HYST 127'C T OI T OI
T HYST
SMI#
*
*
*
*
SMI#
*
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 5-14
Figure 5-15
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W83627THF/W83627THG
T OI
T HYST
SMI#
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 5-16
5.6.4 The W83627THF temperature sensor 2(CPUTIN) and sensor 3(AUXTIN) SMI# interrupt has two modes and it is programmed at CR[4Ch] bit 6.
(1) Comparator Interrupt Mode
Temperature exceeding TO causes an interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the THYST, the interrupt will occur again when the next conversion has completed. If an interrupt event has occurred by exceeding TO and not reset, the interrupts will not occur again. The interrupts will continue to occur in this manner until the temperature goes below THYST. ( Figure 5-17 )
(2) Two-Times Interrupt Mode
Temperature exceeding TO causes an interrupt and then temperature going below THYST will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. Once an interrupt event has occurred by exceeding TO , then reset, if the temperature remains above the THYST , the interrupt will not occur. (Figure 5-18 )
T OI
T OI
T HYST
T HYST
SMI#
*
*
*
*
*
SMI#
*
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 5-17
Figure 5-18
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
5.7 OVT# interrupt mode
The OVT# mode selection bits are at Bank0 Index18h bit4, Bank1 Index52h bit1 and Bank2 Index52h bit1.
(1) Comparator Mode :
Temperature exceeding TO causes the OVT# output activated until the temperature is less than THYST. ( Figure 5-19)
(2) Interrupt Mode:
Temperature exceeding TO causes the OVT# output activated indefinitely until reset by reading temperature sensor registers. Temperature exceeding TO, then OVT# reset, and then temperature going below THYST will also cause the OVT# activated indefinitely until reset by reading temperature sensor registers. Once the OVT# is activated by exceeding TO , then reset, if the temperature remains above THYST , the OVT# will not be activated again.( Figure 5-19)
To
T HYST
OVT# (Comparator Mode; default) OVT# (Interrupt Mode)
*
*
*
*Interrupt Reset when Temperature sensor registers are read
Figure 5-19
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W83627THF/W83627THG
5.8 REGISTERS AND RAM
Address Port and Data Port are set in the register CR60 and CR61 of Logical Device B which is Hardware Monitor Device. The value in CR60 is high byte and that in CR61 is low byte. For example, setting CR60 to 02 and CR61 to 90 cause the Address Port to be 0x295 and Data Port to be 0x296.
5.8.1
Address Port (Port x5h)
Port x5h 00h Bit 6:0 Read/write , Bit 7: Reserved 8 bits
7 6 5 4 3 2 1 0
Address Port: Power on Default Value Attribute: Size:
Data
Bit7: Reserved Bit 6-0: Read/Write
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved (Power On default 0)
Address Pointer (Power On default 00h) A6 A5 A4 A3 A2 A1 A0
5.8.2
Data Port (Port x6h)
Port x6h 00h Read/write 8 bits
7 6 5 4 3 2 1 0
Data Port: Power on Default Value Attribute: Size:
Data
Bit 7-0: Data to be read from or to be written to RAM and Register.
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W83627THF/W83627THG
5.8.3 Configuration Register Index 40h
40h 03h Read/write 8 bits
6 5 4 3 2 1 0
Register Location: Power on Default Value Attribute: Size:
7
START SMI#Enable Reserved INT_Clear Reserved Reserved Reserved INITIALIZATION
Bit 7: A one restores power on default value to some registers. This bit clears itself since the power on default is zero. Bit 6: Reserved Bit 5: Reserved Bit 4: Reserved Bit 3: A one disables the SMI# output without affecting the contents of Interrupt Status Registers. The device will stop monitoring. It will resume upon clearing of this bit. Bit 2: Reserved Bit 1: A one enables the SMI# Interrupt output. Bit 0: A one enables startup of monitoring operations, a zero puts the part in standby mode.
Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike "INT_Clear'' bit.
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W83627THF/W83627THG
5.8.4 Interrupt Status Register 1 Index 41h
41h 00h Read Only 8 bits
7 6 5 4 3 2 1 0
Register Location: Power on Default Value Attribute: Size:
CPUVCORE VIN0 VIN1 AVCC(pin 114) SYSTIN CPUTIN SYSFANIN CPUFANIN
Bit 7: A one indicates the fan count limit of CPUFANIN has been exceeded. Bit 6: A one indicates the fan count limit of SYSFANIN has been exceeded. Bit 5: A one indicates a High limit of CPUTIN temperature has been exceeded. Bit 4: A one indicates a High limit of SYSTIN temperature has been exceeded . Bit 3: A one indicates a High or Low limit of AVCC(pin 114) has been exceeded. Bit 2: A one indicates a High or Low limit of VIN1 has been exceeded. Bit 1: A one indicates a High or Low limit of VIN0 has been exceeded. Bit 0: A one indicates a High or Low limit of CPUVCORE has been exceeded.
5.8.5
Interrupt Status Register 2 Index 42h
42h 00h Read Only 8 bits
7 6 5 4 3 2 1 0
Register Location: Power on Default Value Attribute: Size:
VIN2 Reserved Reserved AUXFANIN CaseOpen AUXTIN TAR1 TAR2
Bit 7: A one indicates that the CPUTIN temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFanTM.
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W83627THF/W83627THG
Bit 6: A one indicates that the SYSTIN temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFanTM. Bit 5: A one indicates a High or Low limit of AUXTIN temperature has been exceeded. Bit 4: A one indicates case has been opened. Bit 3: A one indicates the fan count limit of AUXFANIN has been exceeded . Bit 2: Reserved. Bit 1: Reserved. Bit 0: A one indicates a High or Low limit of VIN2 has been exceeded.
5.8.6
SMI# Mask Register 1 Index 43h
43h FEh Read/Write 8 bits
7 6 5 4 3 2 1 0
Register Location: Power on Default Value Attribute: Size:
CPUVCORE VIN0 VIN1 AVCC (pin 114) SYSTIN CPUTIN SYSFANIN CPUFANIN
Bit 7-0: A one disables the corresponding interrupt status bit for SMI interrupt.
5.8.7
SMI# Mask Register 2 Index 44h
44h FFh Read/Write 8 bits
7 6 5 4 3 2 1 0
Register Location: Power on Default Value Attribute: Size:
VIN2 Reserved Reserved AUXFANIN CaseOpen AUXTIN TAR1 TAR2
Bit 7-0: A one disables the corresponding interrupt status bit for SMI interrupt.
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W83627THF/W83627THG
5.8.8 5.8.9 Reserved Register Index 45h--46h Fan Divisor Register I Index 47h
47h Read/Write 8 bits
7 6 5 4 3 2 1 0
Register Location: Attribute: Size:
Power on Default Value: 5Fh
Reserved Reserved Reserved Reserved SYSFANINDIV_B0 SYSFANINDIV_B1 CPUFANINDIV_B0 CPUFANINDIV_B1
Bit 7-6: CPUFANIN Divisor bit1:0 . Bit 5-4: SYSFANIN Divisor bit1:0.
Note : Please refer to Bank0 CR[5Dh] , Fan divisor table.
5.8.10 Value RAM Index 20h- 3Fh
ADDRESS A6-A0 DESCRIPTION
20h 21h 22h 23h 24h 25h 26h 27h 28h
CPUVCORE reading VIN0 reading VIN1 reading AVCC(pin 114)reading VIN2 reading Reserved Reserved SYSTIN temperature sensor reading SYSFANIN reading
Note: This location stores the number of counts of the internal clock per revolution.
CPUFANIN reading 29h
Note: This location stores the number of counts of the internal clock per revolution.
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W83627THF/W83627THG
Value RAM Index 20h- 3Fh, continued
ADDRESS A6-A0
DESCRIPTION
2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh
CPUVCORE High Limit (Power on default value is 1.75V) CPUVCORE Low Limit (Power on default value is 0V) VIN0 High Limit VIN0 Low Limit VIN1 High Limit VIN1 Low Limit AVCC(pin 114) High Limit AVCC(pin 114) Low Limit VIN2 High Limit VIN2 Low Limit Reserved Reserved Reserved Reserved SYSTIN temperature sensor High Limit SYSTIN temperature sensor Hysteresis Limit SYSFANIN Fan Count Limit
Note: It is the number of counts of the internal clock for the Low Limit of the fan speed.
CPUFANIN Fan Count Limit 3Ch
Note: It is the number of counts of the internal clock for the Low Limit of the fan speed.
AUXFANIN Fan Count Limit 3Dh 3E- 3Fh
Note: It is the number of counts of the internal clock for the Low Limit of the fan speed.
Reserved
Setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means interrupts will never be generated except the case when voltages go below the low limits.
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W83627THF/W83627THG
5.8.11 Device ID Register - Index 49h
Register Location: Power on Default Value Attribute: Size:
7
49h 03h bit<7:1> Read Only; bit<0> Read/Write 8 bits
6 5 4 3 2 1 0
Reserved
DID<6:0>
Bit 7-1: Read Only - Device ID<6:0> Bit 0 :Reserved.
5.8.12 Reserved Register Index 4Ah 5.8.13 Fan Divisor Register II - Index 4Bh
Register Location: Power on Default Value Attribute: Size:
7 6
4Bh <7:0> 44h. Read/Write 8 bits
5 4 3 2 1 0
Reserved Reserved Reserved Reserved ADCOVSEL ADCOVSEL AUXFANINDIV_B0 AUXFANINDIV_B1
Bit 7-6:AUXFANIN speed divisor.Please refer to Bank0 CR[5Dh] , Fan divisor table. Bit 5-4: Select A/D Converter Clock Input. <5:4> = 00 - default. ADC clock select 22.5 Khz. <5:4> = 01- ADC clock select 5.6 Khz. (22.5K/4) <5:4> = 10 - ADC clock select 1.4Khz. (22.5K/16) <5:4> = 11 - ADC clock select 0.35 Khz. (22.5K/64) Bit 3-2: These two bits should be set to 01h. The default value is 01h. Bit 1-0: Reserved.
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
5.8.14 SMI#/OVT# Control Register- Index 4Ch
Register Location: Power on Default Value Attribute: Size:
7
4Ch 18h Read/Write 8 bits
6 5 4 3 2 1 0
Reserved Reserved OVTPOL DIS_OVT2 DIS_OVT3 EN_T1_ONE T2T3_INTMode Reserved
Bit 7: Reserved. User Defined. Bit 6: Set to 1, the SMI# output type of Temperature CPUTIN/AUXTIN is set to Comparator Interrupt mode. Set to 0, the SMI# output type is set to Two-Times Interrupt mode. (default 0) Bit 5: Set to 1, the SMI# output type of temperature SYSTIN is One-Time interrupt mode. Set to 0, the SMI# output type is Two-Times interrupt mode. Bit 4: Disable temperature sensor AUXTIN over-temperature (OVT) output if set to 1. Set 0, enable AUXTIN OVT output through pin OVT#. Bit 3: Disable temperature sensor CPUTIN over-temperature (OVT) output if set to 1. Set 0, enable CPUTIN OVT output through pin OVT#. Bit 2: Over-temperature polarity. Write 1, OVT# active high. Write 0, OVT# active low. Default 0. Bit 1: Reserved. Bit 0: Reserved.
5.8.15 FAN IN/OUT and BEEP Control Register- Index 4Dh
Register Location: Power on Default Value Attribute: Size:
7
4Dh 15h Read/Write 8 bits
6 5 4 3 2 1 0
FANINC1 FANOPV1 FANINC2 FANOPV2 FANINC3 FANOPV3 Reserved Reserved
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W83627THF/W83627THG
Bit 7~6: Reserved. Bit 5: AUXFANIN output value if FANINC3 sets to 0. Write 1, pin 5 generates a logic high signal. Write 0, pin 5 generates a logic low signal. This bit is default 0. Bit 4: AUXFANIN Input Control. Set to 1, pin 5 acts as FAN tachometer input, which is default value. Set to 0, this pin 5 acts as FAN control signal and the output value of FAN control is set by this register bit 5. Bit 3: CPUFANIN output value if FANINC2 sets to 0. Write 1, then pin 112 always generate logic high signal. Write 0, pin 112 always generates logic low signal. This bit default 0. Bit 2: CPUFANIN Input Control. Set to 1, pin 112 acts as FAN tachometer input, which is default value. Set to 0, this pin 112 acts as FAN control signal and the output value of FAN control is set by this register bit 3. Bit 1: SYSFANIN output value if FANINC1 sets to 0. Write 1, then pin 113 always generate logic high signal. Write 0, pin 113 always generates logic low signal. This bit default 0. Bit 0: SYSFANIN Input Control. Set to 1, pin 113 acts as FAN tachometer input, which is default value. Set to 0, this pin 113 acts as FAN control signal and the output value of FAN control is set by this register bit 1.
5.8.16 Register 50h ~ 5Fh Bank Select Register - Index 4Eh
Register Location: Power on Default Value Attribute: Size:
7 6
4Eh 80h Read/Write 8 bits
5 4 3 2 1 0
BANKSEL0 BANKSEL1 BANKSEL2 Reserved Reserved Reserved Reserved HBACS
Bit 7: HBACS- High byte access. Set to 1, access Register 4Fh high byte register. Set to 0, access Register 4Fh low byte register. Default 1. Bit 6-3: Reserved. This bit should be set to 0. Bit 2-0: Index ports 0x50~0x5F Bank select. Set to 0, select Bank0. Set to 1, select Bank1. Set to 2, select Bank2.
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
5.8.17 Winbond Vendor ID Register - Index 4Fh
Register Location: Power on Default Value Attribute: Size:
15
4Fh <15:0> = 5CA3h Read Only 16 bits
8 7 0
VIDH
VIDL
Bit 15-8: Vendor ID High Byte if CR4E.bit7=1.Default 5Ch. Bit 7-0: Vendor ID Low Byte if CR4E.bit7=0. Default A3h.
5.8.18 Winbond Test Register -- Index 50h - 55h (Bank 0) 5.8.19 BEEP Control Register 1-- Index 56h (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7
56h 00h Read/Write 8 bits
6 5 4 3 2 1 0
EN_VCORE_BP EN_VIN0_BP EN_VIN1_BP EN_AVCC_BP EN_SYSTIN_BP EN_CPUTIN_BP EN_SYSFANIN_BP EN_CPUFANIN_BP
Bit 7: BEEP output control for CPUFANIN if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 6: BEEP output control for SYSFANIN if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 5: BEEP output control for temperature CPUTIN if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 4: BEEP output control for temperature SYSTIN if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 3: BEEP output control for AVCC(pin 114) if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value.
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W83627THF/W83627THG
Bit 2: BEEP output control for VIN1 if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 1: BEEP output control for VIN0 if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 0: BEEP output control for CPUVCORE if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value.
5.8.20 BEEP Control Register 2-- Index 57h (Bank 0)
Register Location: Attribute: Size: 57h Read/Write 8 bits
7 6 5 4 3 2 1 0
Power on Default Value 80h
EN_VIN2_BP Reserved Reserved EN_AUXFANIN_BP EN_CASO_BP EN_AUXTIN_BP Reserved EN_GBP
Bit 7: Global BEEP Control. Write 1, enable global BEEP output. Default 1. Write 0, disable all BEEP output. Bit 6: Reserved. Bit 5: BEEP output control for temperature AUXTIN if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 4: BEEP output control for case open if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 3: BEEP output control for AUXFANIN if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 2-1: Reserved. Bit 0: BEEP output control for VIN1 if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value.
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
5.8.21 Chip ID -- Index 58h (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7 6
58h 90h Read Only 8 bits
5 4 3 2 1 0
CHIPID
Bit 7-0: Winbond Chip ID number. Read this register will return 90h.
5.8.22 Diode Selection Register
Register Location: Power on Default Value Attribute: Size:
7
-- Index 59h (Bank 0)
59h 70h Read/Write 8 bits
6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved SELPIIV1 SELPIIV2 SELPIIV3 Reserved
Bit 7 : Reserved Bit 6: Diode mode selection of temperature AUXTIN if index 5Dh bit3 is 1. Set this bit to 1, select Pentium II CPU compatible thermal diode. Set this bit to 0, select 2N3904 bipolar diode. Bit 5: Diode mode selection of temperature CPUTIN if index 5Dh bit2 is 1. Set this bit to 1, select Pentium II CPU compatible thermal diode. Set this bit to 0, select 2N3904 bipolar diode. Bit 4: Diode mode selection of temperature SYSTIN if index 5Dh bit1 is 1. Set this bit to 1, select Pentium II CPU compatible thermal diode. Set this bit to 0, select 2N3904 bipolar diode. Bit 3-0: Reserved
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W83627THF/W83627THG
5.8.23 Reserved -- Index 5Ah (Bank 0) 5.8.24 Reserved -- Index 5Bh (Bank 0) 5.8.25 Reserved -- Index 5Ch (Bank 0) 5.8.26 VBAT Monitor Control Register -- Index 5Dh (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7
5Dh 00h Read/Write 8 bits
6 5 4 3 2 1 0
EN_VBAT_MNT DIODES1 DIODES2 DIODES3 Reserved FANDIV1_B2 FANDIV2_B2 FANDIV3_B2
Bit 7: AUXFANIN divisor Bit2. Bit 6: CPUFANIN divisor Bit2. Bit 5: SYSFANIN divisor Bit2. Bit 4: Reserved. Bit 3: Sensor type selection of AUXTIN. Set to 1, select diode sensor. Set to 0, select thermistor sensor. Bit 2: Sensor type selection of CPUTIN. Set to 1, select diode sensor. Set to 0, select thermistor sensor. Bit 1: Sensor type selection of SYSTIN. Set to 1, select diode sensor. Set to 0, select thermistor sensor. Bit 0: Set to 1, enable battery voltage monitor. Set to 0, disable battery voltage monitor. After set this bit from 0 to 1, the monitored value will be updated to the VBAT reading value register after one monitor cycle time.
Fan divisor table :
BIT 2 BIT 1 BIT 0 FAN DIVISOR BIT 2 BIT 1 BIT 0 FAN DIVISOR
0 0 0 0
0 0 1 1
0 1 0 1
1 2 4 8 Table 5-3
1 1 1 1
0 0 1 1
0 1 0 1
16 32 64 128
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W83627THF/W83627THG
5.8.27 Reserved Register --5Eh (Bank 0) 5.8.28 Reserved Register --5Fh (Bank 0) 5.8.29 CPUTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 1)
Register Location: Attribute: Size: 50h Read Only 8 bits
7 6 5 4 3 2 1 0
TEMP<8:1>
Bit 7: Temperature <8:1> of CPUTIN sensor, which is high byte, means 1C.
5.8.30 CPUTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 1)
Register Location: Attribute: Size: 51h Read Only 8 bits
7 6 5 4 3 2 1 0
Reserved
TEMP<0>
Bit 7: Temperature <0> of CPUTIN sensor, which is low byte, means 0.5C. Bit 6-0: Reserved.
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W83627THF/W83627THG
5.8.31 CPUTIN Temperature Sensor Configuration Register - Index 52h (Bank 1)
Register Location: Power on Default Value Size:
7 6
52h 00h 8 bits
5 4 3 2 1 0
STOP OVTMOD Reserved FAULT FAULT Reserved Reserved Reserved
Bit 7-5: Read - Reserved. This bit should be set to 0. Bit 4-3: Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping due to noise. Bit 2: Read - Reserved. This bit should be set to 0. Bit 1: Read/Write - OVT# mode select. This bit default is set to 0, which is compared mode. When set to 1, interrupt mode will be selected. Bit 0: Read/Write - When set to 1 the sensor will stop monitor.
5.8.32 CPUTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 1)
Register Location: Power on Default Value Attribute: Size:
7 6
53h 4Bh Read/Write 8 bits
5 4 3 2 1 0
THYST<8:1>
Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C.
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5.8.33 CPUTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 1)
Register Location: Power on Default Value Attribute: Size:
7
54h 00h Read/Write 8 bits
6 5 4 3 2 1 0
Reserved
THYST<0>
Bit 7: Hysteresis temperature bit 0, which is low Byte. Bit 6-0: Reserved.
5.8.34 CPUTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank1)
Register Location: Power on Default Value Attribute: Size:
7 6
55h 50h Read/Write 8 bits
5 4 3 2 1 0
TOVF<8:1>
Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C.
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5.8.35 CPUTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank 1)
Register Location: Power on Default Value Attribute: Size:
7
56h 00h Read/Write 8 bits
6 5 4 3 2 1 0
Reserved
TOVF<0>
Bit 7: Over-temperature bit 0, which is low Byte. Bit 6-0: Reserved.
5.8.36 AUXTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 2)
Register Location: Attribute: Size: 50h Read Only 8 bits
7 6 5 4 3 2 1 0
TEMP<8:1>
Bit 7: Temperature <8:1> of sensor 2, which is high byte, means 1C.
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5.8.37 AUXTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 2)
Register Location: Attribute: Size: 51h Read Only 8 bits
7 6 5 4 3 2 1 0
Reserved
TEMP<0>
Bit 7: Temperature <0> of sensor3, which is low byte, means 0.5C. Bit 6-0: Reserved.
5.8.38 AUXTIN Temperature Sensor Configuration Register - Index 52h (Bank 2)
Register Location: Power on Default Value Size:
7
52h 00h 8 bits
6 5 4 3 2 1 0
STOP OVTMOD Reserved FAULT FAULT Reserved Reserved Reserved
Bit 7-5: Read - Reserved. This bit should be set to 0. Bit 4-3: Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping due to noise. Bit 2: Read - Reserved. This bit should be set to 0. Bit 1: Read/Write - OVT# mode select. This bit default is set to 0, which is compared mode. When set to 1, interrupt mode will be selected. Bit 0: Read/Write - When set to 1 the sensor will stop monitor.
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5.8.39 AUXTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 2)
Register Location: Power on Default Value Attribute: Size:
7
53h 4Bh Read/Write 8 bits
6 5 4 3 2 1 0
THYST<8:1>
Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C.
5.8.40 AUXTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 2)
Register Location: Power on Default Value Attribute: Size:
7
54h 00h Read/Write 8 bits
6 5 4 3 2 1 0
Reserved
THYST<0>
Bit 7: Hysteresis temperature bit 0, which is low Byte. Bit 6-0: Reserved.
5.8.41 AUXTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank 2)
Register Location: Power on Default Value Attribute: Size: 55h 50h Read/Write 8 bits
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7 6 5 4 3 2 1 0
TOVF<8:1>
Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C.
5.8.42 AUXTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank 2)
Register Location: Power on Default Value Attribute: Size:
7
56h 00h Read/Write 8 bits
6 5 4 3 2 1 0
Reserved
TOVF<0>
Bit 7: Over-temperature bit 0, which is low Byte. Bit 6-0: Reserved.
5.8.43 Interrupt Status Register 3 -- Index 50h (BANK4)
Register Location: Power on Default Value Attribute: Size:
7
50h 00h Read Only 8 bits
6 5 4 3 2 1 0
5VSB VBAT TAR3 Reserved Reserved Reserved Reserved Reserved
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Bit 7-3: Reserved. Bit 2: A one indicates that the AUXTIN temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFanTM . Bit 1: A one indicates a High or Low limit of VBAT has been exceeded. Bit 0: A one indicates a High or Low limit of 5VSB has been exceeded.
5.8.44 SMI# Mask Register 3 -Register Location: Power on Default Value Attribute: Size: 51h FFh
Index 51h (BANK 4)
Read/Write 8 bits
7 6 5 4 3 2 1 0
5VSB VBAT Reserved Reserved TAR3 Reserved Reserved Reserved
Bit 7-5: Reserved. Bit 4: A one disables the corresponding interrupt status bit for SMI interrupt. Bit 2-3: Reserved. Bit 1: A one disables the corresponding interrupt status bit for SMI interrupt. Bit 0: A one disables the corresponding interrupt status bit for SMI interrupt.
5.8.45 Reserved Register -- Index 52h (Bank 4) 5.8.46 BEEP Control Register 3-- Index 53h (Bank 4)
Register Location: Power on Default Value Attribute: Size:
7
53h 00h Read/Write 8 bits
6 5 4 3 2 1 0
EN_5VSB_BP EN_VBAT_BP Reserved Reserved Reserved EN_USER_BP Reserved Reserved
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Bit 7-6: Reserved. Bit 5: User define BEEP output function. Write 1, the BEEP is always active. Write 0, this function is inactive. (Default 0) Bit 4-2: Reserved. Bit 1: BEEP output control for VBAT if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 0: BEEP output control for 5VSB if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value.
5.8.47 SYSTIN Temperature Sensor Offset Register -- Index 54h (Bank 4)
Register Location: Power on Default Value Attribute: Size:
7 6
54h 00h Read/Write 8 bits
5 4 3 2 1 0
OFFSET<7:0>
Bit 7-0: SYSTIN temperature offset value. The value in this register will be added to the monitored value so that the reading value will be the sum of the monitored value and the offset value.
5.8.48 CPUTIN Temperature Sensor Offset Register -- Index 55h (Bank 4)
Register Location: Power on Default Value Attribute: Size:
7 6
55h 00h Read/Write 8 bits
5 4 3 2 1 0
OFFSET<7:0>
Bit 7-0: CPUTIN temperature offset value. The value in this register will be added to the monitored value so that the reading value will be the sum of the monitored value and the offset value.
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5.8.49 AUXTIN Temperature Sensor Offset Register -- Index 56h (Bank 4)
Register Location: Power on Default Value Attribute: Size:
7
56h 00h Read/Write 8 bits
6 5 4 3 2 1 0
OFFSET<7:0>
Bit 7-0: AUXTIN temperature offset value. The value in this register will be added to the monitored value so that the reading value will be the sum of the monitored value and the offset value.
5.8.50 Reserved Register -- Index 57h--58h (Bank4) 5.8.51 Real Time Hardware Status Register I -- Index 59h (Bank 4)
Register Location: Power on Default Value Attribute: Size:
7 6
59h 00h Read Only 8 bits
5 4 3 2 1 0
VCORE_STS VIN0_STS VIN1_STS AVCC_STS SYSTIN_STS CPUTIN_STS SYSFANIN_STS CPUFANIN_STS
Bit 7: CPUFANIN Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is in the limit range. Bit 6: SYSFANIN Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is in the limit range. Bit 5: CPUTIN temperature sensor status. Set 1, the temperature exceeds the over-temperature limit value. Set 0, the temperature is in under the hysteresis value. Bit 4: SYSTIN temperature sensor status. Set 1, the temperature exceeds the over-temperature limit value. Set 0, the temperature is in under the hysteresis value. Bit 3: AVCC Voltage Status. Set 1, the voltage of AVCC is over the limit value. Set 0, the voltage of AVCC is in the limit range.
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Bit 2: VIN1 Voltage Status. Set 1, the voltage of VIN1 is over the limit value. Set 0, the voltage of VIN1 is in the limit range. Bit 1: VIN0 Voltage Status. Set 1, the voltage of VIN0 is over the limit value. Set 0, the voltage of VIN0 is in the limit range. Bit 0: VCORE Voltage Status. Set 1, the voltage of VCORE is over the limit value. Set 0, the voltage of VCORE is in the limit range.
5.8.52 Real Time Hardware Status Register II -- Index 5Ah (Bank 4) Register Location: 5Ah Power on Default Value 00h Attribute: Read Only Size: 8 bits
7 6 5 4 3 2 1 0
VIN2_STS Reserved Reserved AUXFANIN_STS CASE_STS AUXTIN_STS TAR1_STS TAR2_STS
Bit 7: Smart CPUFANIN warning status. Set 1, the CPUTIN temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFanTM. Set 0, the temperature does not reach the warning range yet. Bit 6: Smart SYSFANIN warning status. Set 1, the SYSTIN temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFanTM. Set 0, the temperature does not reach the warning range yet. Bit 5: AUXTIN temperature sensor status. Set 1, the temperature exceeds the over-temperature limit value. Set 0, the temperature is in under the hysteresis value. Bit 4: Case Open Status. Set 1, the case open is detected and latched. Set 0, the case is not latched open. Bit 3: CPUFANIN Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is in the limit range. Bit 2-1: Reserved. Bit 0: VIN2 Voltage Status. Set 1, the voltage of VIN2 is over the limit value. Set 0, the voltage of VIN2 is in the limit range.
5.8.53 Real Time Hardware Status Register III -- Index 5Bh (Bank 4)
Register Location: Power on Default Value Attribute: Size: 5Bh 00h Read Only 8 bits
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7
6
5
4
3
2
1
0
5VSB_STS VBAT_STS TAR3 Reserved Reserved Reserved Reserved Reserved
Bit 7-2: Reserved. Bit 2: Smart AUXFANIN warning status. Set 1, the AUXTIN temperature has been over temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFanTM. temperature does not reach the warning range yet. Bit 1: VBAT Voltage Status. Set 1, the voltage of VBAT is over the limit value. Set 0, the VBAT is during the limit range. Bit 0: 5VSB Voltage Status. Set 1, the voltage of 5VSB is over the limit value. Set 0, the 5VSB is in the limit range.
the target Set 0, the voltage of voltage of
5.8.54 Reserved Register -- Index 5Ch (Bank 4) 5.8.55 Reserved Register -- Index 5Dh (Bank 4) 5.8.56 Value RAM 2 Index 50h - 5Ah (BANK 5)
ADDRESS A6-A0 DESCRIPTION
50h 51h 52h 53h 54h 55h 56h 57h
5VSB reading VBAT reading. The reading is meaningless if EN_VBAT_MNT bit(CR5D bit0) is not set. Reserved Reserved 5VSB High Limit 5VSB Low Limit. VBAT High Limit VBAT Low Limit
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5.8.57 Winbond Test Register -- Index 50h (Bank 6) 5.8.58 Reserved Register--Index00h (Bank 0) 5.8.59 SYSFANOUT Output Value Control Register-- 01h (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7 6
01h FFh Read/Write 8 bits
5 4 3 2 1 0
Reserved Reserved Reserved Reserved SYSFANOUT Value
Bit 7-4: SYSFANOUT voltage control.
OUTPUT Voltage = AVCC *
If AVCC= 5V , output voltage table is
BIT 7 BIT 6 BIT 5 BIT 4 OUTPUT VOLTAGE
FANOUT 16
OUTPUT VOLTAGE
BIT 7
BIT 6
BIT 5
BIT 4
0 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 0.31 0.63 0.97 1.25 1.56 1.88 2.19
1 1 1 1 1 1 1 1 Table 5-4 .
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
2.50 2.81 3.13 3.44 3.75 4.06 4.38 4.69
Note. The accuracy of FANOUT voltage is +/- 0.16 V.
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5.8.60 Reserved Register--Index02h (Bank 0) 5.8.61 CPUFANOUT Output Value Control Register-- 03h (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7 6
03h FFh Read/Write 8 bits
5 4 3 2 1 0
Reserved Reserved Reserved Reserved CPUFANOUT Value
Bit 7-4: CPUFANOUT voltage control.
OUTPUT Voltage = AVCC *
Note: See the Table 5-4
FANOUT 16
5.8.62 FAN Configuration Register I -- Index 04h (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7
04h 00h Read/Write 8 bits
6 5 4 3 2 1 0
Reserved Reserved SYSFAN_Mode SYSFAN_Mode CPUFAN_Mode CPUFAN_Mode Reserved Reserved
Bit7-6: Reserved Bit5-4: CPUFANOUT mode control. Set 00, CPUFANOUT is as Manual Mode. (Default). Set 01, CPUFANOUT is as Thermal Cruise Mode.
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Set 10, CPUFANOUT is as Fan Speed Cruise Mode. Set 11, reserved and no function. Bit3-2: SYSFANOUT mode control. Set 00, SYSFANOUT is as Manual Mode. (Default). Set 01, SYSFANOUT is as Thermal Cruise Mode. Set 10, SYSFANOUT is as Fan Speed Cruise Mode. Set 11, reserved and no function. Bit 1-0:Reserved.
5.8.63 SYSTIN Target Temperature Register/ SYSFANIN Target Speed Register -- Index 05h (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7 6 5 4
05h 00h Read/Write 8 bits
3 2 1 0
Target Temperature / Target Speed
(1).When at Thermal Cruise mode: Bit7: Reserved. Bit6-0: SYSTIN Target Temperature. (2).When at Fan Speed Cruise mode: Bit7-0: SYSFANIN Target Speed.
5.8.64 CPUTIN Target Temperature Register/ CPUFANIN Target Speed Register -- Index 06h (Bank 0)
Register Location: Power on Default Value Attribute: Size: 06h 00h Read/Write 8 bits
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7
6
5
4
3
2
1
0
Target Temperature / Target Speed
(1).When at Thermal Cruise mode: Bit7: Reserved. Bit6-0: CPUTIN Target Temperature. (2).When at Fan Speed Cruise mode: Bit7-0: CPUFANIN Target Speed.
5.8.65 Tolerance of Target Temperature or Target Speed Register -- Index 07h (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7 6 5 4
07h 00h Read/Write 8 bits
3 2 1 0
SYSTIN Target Temperature Tolerance / SYSFANIN Target Speed Tolerance CPUTIN Target Temperature Tolerance / CPUFANIN Target Speed Tolerance
(1).When at Thermal Cruise mode: Bit7-4: Tolerance of CPUTIN Target Temperature. Bit3-0: Tolerance of SYSTIN Target Temperature. (2).When at Fan Speed Cruise mode: Bit7-4: Tolerance of CPUFANIN Target Speed. Bit3-0: Tolerance of SYSFANIN Target Speed.
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5.8.66 SYSFANOUT Stop Value Register -- Index 08h (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7 6 5
08h 01h Read/Write 8 bits
4 3 2 1 0
Reserved Reserved Reserved Reserved SYSFANOUT Stop Value
When at Thermal Cruise mode, SYSFANOUT voltage will decrease to this register value. This register should be written a non-zero minimum output value.
5.8.67 CPUFANOUT Stop Value Register -- 09h (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7 6
09h 01h Read/Write 8 bits
5 4 3 2 1 0
Reserved Reserved Reserved Reserved CPUFANOUT Stop Value
When at Thermal Cruise mode, CPUFANOUT voltage will decrease to this register value. This register should be written a non-zero minimum output value.
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5.8.68 SYSFANOUT Start-up Value Register -- Index 0Ah (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7 6 5
0Ah 01h Read/Write 8 bits
4 3 2 1 0
Reserved Reserved Reserved Reserved SYSFANOUT Start-up Value
When at Thermal Cruise mode, SYSFANOUT voltage will increase from 0 to this register value to provide a minimum value to turn on the fan.
5.8.69 CPUFANOUT Start-up Value Register -- Index 0Bh (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7 6 5
0Bh 01h Read/Write 8 bits
4 3 2 1 0
Reserved Reserved Reserved Reserved CPUFANOUT Start-up Value
When at Thermal Cruise mode, CPUFANOUT voltage will increase from 0 to this register value to provide a minimum value to turn on the fan.
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5.8.70 SYSFANOUT Stop Time Register -- Index 0Ch (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7 6
0Ch 3Ch Read/Write 8 bits
5 4 3 2 1 0
SYSFANOUT Stop Time
When at Thermal Cruise mode, this register determines the time of which SYSFANOUT voltage is from stop value to 0. The unit of this register is 0.1 second. The default time is 6 seconds.
5.8.71 CPUFANOUT Stop Time Register -- Index 0Dh (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7 6
0Dh 3Ch Read/Write 8 bits
5 4 3 2 1 0
CPUFANOUT Stop Time
When at Thermal Cruise mode, this register determines the time of which CPUFANOUT voltage is from stop value to 0. The unit of this register is 0.1 second. The default time is 6 seconds.
5.8.72 Fan Output Step Down Time Register -- Index 0Eh (Bank 0)
Register Location: Power on Default Value Attribute: Size: 0Eh 0Ah Read/Write 8 bits
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7 6 5 4 3 2 1 0
FANOUT Value Step Down Time
This register determines the speed of FANOUT decreasing the voltage in Smart Fan Control mode. The Unit is 1.6 second.
5.8.73 Fan Output Step Up Time Register -- Index 0Fh (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7 6 5
0Fh 0Ah Read/Write 8 bits
4 3 2 1 0
FANOUT Value Step Up Time
This register determines the speed of FANOUT increasing the voltage in Smart Fan Control mode. The Unit is 1.6 second
5.8.74 Reserved Register--Index10h (Bank 0) 5.8.75 AUXFANOUT Output Value Control Register-- 11h (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7 6
11h FFh Read/Write 8 bits
5 4 3 2 1 0
Reserved Reserved Reserved Reserved AUXFANOUT Value
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Bit 7-4: AUXFANOUT voltage control.
OUTPUT Voltage = AVCC *
Note: See the Table 5-4
FANOUT 16
5.8.76 FAN Configuration Register II -- Index 12h (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7 6
12h 00h Read/Write 8 bits
5 4 3 2 1 0
Reserved AUXFANOUT_Mode AUXFANOUT_Mode AUXFANOUT_MIN_Volt CPUFANOUT_MIN_Volt SYSFANOUT_MIN_Volt Reserved Reserved
Bit7-6: Reserved Bit 5: Set 1, SYSFANOUT voltage will decrease to and keep the value set in Index 08h when temperature goes below target range. This is to maintain the fan speed in a minimum value. Set 0, SYSFANOUT duty cycle will decrease to 0 when temperature goes below target range. Bit 4: Set 1, CPUFANOUT duty cycle will decrease to and keep the value set in Index 09h when temperature goes below target range. This is to maintain the fan speed in a minimum value. Set 0, CPUFANOUT duty cycle will decrease to 0 when temperature goes below target range. Bit 3: Set 1, AUXFANOUT duty cycle will decrease to and keep the value set in Index 15h when temperature goes below target range. This is to maintain the fan speed in a minimum value. Set 0, AUXFANOUT duty cycle will decrease to 0 when temperature goes below target range. Bit2-1: AUXFANOUT mode control. Set 00, AUXFANOUT is as Manual Mode. (Default). Set 01, AUXFANOUT is as Thermal Cruise Mode. Set 10, AUXFANOUT is as Fan Speed Cruise Mode. Set 11, reserved and no function. Bit 0:Reserved.
5.8.77 AUXTIN Target Temperature Register/ AUXFANIN Target Speed Register -- Index 13h (Bank 0) Register Location: 13h Power on Default Value 00h
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Attribute: Size:
7 6 5 4
Read/Write 8 bits
3 2 1 0
Target Temperature / Target Speed
(1).When at Thermal Cruise mode: Bit7: Reserved. Bit6-0: AUXTIN Target Temperature. (2).When at Fan Speed Cruise mode: Bit7-0: AUXFANIN Target Speed.
5.8.78 Tolerance of Target Temperature or Target Speed Register -- Index 14h (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7 6 5 4
14h 00h Read/Write 8 bits
3 2 1 0
AUXTIN Target Temperature Tolerance / AUXFANIN Target Speed Tolerance Reserved
(1).When at Thermal Cruise mode: Bit3-0: Tolerance of AUXTIN Target Temperature. (2).When at Fan Speed Cruise mode: Bit3-0: Tolerance of AUXFANIN Target Speed.
5.8.79 AUXFANOUT Stop Value Register -- Index 15h (Bank 0)
Register Location: Power on Default Value Attribute: Size: 15h 01h Read/Write 8 bits
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7
6
5
4
3
2
1
0
Reserved Reserved Reserved Reserved AUXFANOUT Stop Value
When at Thermal Cruise mode, AUXFANOUT value will decrease to register value. This register should be written a non-zero minimum output value.
5.8.80 AUXFANOUT Start-up Value Register -- Index 16h (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7 6 5
16h 01h Read/Write 8 bits
4 3 2 1 0
Reserved Reserved Reserved Reserved AUXFANOUT Start-up Value
When at Thermal Cruise mode, AUXFANOUT value will increase from 0 to this register value to provide a minimum voltage to turn on the fan.
5.8.81 AUXFANOUT Stop Time Register -- Index 17h (Bank 0)
Register Location: Power on Default Value Attribute: Size: 17h 3Ch Read/Write 8 bits
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7
6
5
4
3
2
1
0
AUXFANOUT Stop Time
When at Thermal Cruise mode, this register determines the time of which AUXFANOUT voltage is from stop value to 0. The unit of this register is 0.1 second. The default time is 6 seconds.
5.8.82 VRM & OVT Configuration Register -- Index 18h (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7
18h 43h Read/Write 8 bits
6 5 4 3 2 1 0
VCORE_AD_SEL Reserved Reserved Reserved OVT1_Mode Reserved DIS_OVT1 Reserved
Bit 7: Reserved. Bit 6: Set to 1, disable temperature sensor SYSTIN over-temperature (OVT#) output. Set to 0, enable the SYSTIN OVT# output. Bit 5: Reserved. Bit 4: SYSTIN OVT# mode select. This bit default is set to 0, which is compared mode. When set to 1, interrupt mode will be selected. Bit 3-1: Reserved. Bit 0: CPUVCORE pin voltage detection method selection. Set to 1, VRM9 formula is selected. Set to 0, VRM8 formula is selected. This bit default value is 1.
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5.8.83 Reserved -- Index 19h (Bank 0) 5.8.84 User Defined Register -- Index 1A- 1Bh (Bank 0)
Register Location: Power on Default Value Attribute: Size:
7
1A-1Bh FFh Read/Write 8 bits
6 5 4 3 2 1 0
User-defined User-defined User-defined User-defined User-defined User-defined User-defined User-defined
Bit 7-0: User can write any value into these bits and read.
5.8.85 Reserved Register-- Index 1Ch-1Fh (Bank 0)
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6. PLUG AND PLAY CONFIGURATION
The W83627THF uses Compatible PNP protocol to access configuration registers for setting up different types of configurations. In W83627THF, there are eleven Logical Devices (from Logical Device 0 to Logical Device B with the exception of logical device 4 for backward compatibility) which correspond to eleven individual functions: FDC (logical device 0), PRT (logical device 1), UART1 (logical device 2), UART2 (logical device 3), KBC (logical device 5), GPIO,5 (logical device 7), GPIO2 (logical device 8), GPIO3,4 (logical device 9), ACPI ((logical device A), and hardware monitor (logical device B). Each Logical Device has its own configuration registers (above CR30). Host can access those registers by writing an appropriate logical device number into logical device select register at CR7.
6.1
6.1.1
Compatible PnP
Extended Function Registers
In Compatible PnP, there are two ways to enter Extended Function and read or write the configuration registers. HEFRAS (CR26 bit 6) can be used to select one out of these two methods of entering the Extended Function mode as follows:
HEFRAS ADDRESS AND VALUE
0 1
write 87h to the location 2Eh twice write 87h to the location 4Eh twice
After Power-on reset, the value on RTSA# (pin 43) is latched by HEFRAS of CR26. In Compatible PnP, a specific value (87h) must be written twice to the Extended Functions Enable Register (I/O port address 2Eh or 4Eh). Secondly, an index value (02h, 07h-FFh) must be written to the Extended Functions Index Register (I/O port address 2Eh or 4Eh same as Extended Functions Enable Register) to identify which configuration register is to be accessed. The designer can then access the desired configuration register through the Extended Functions Data Register (I/O port address 2Fh or 4Fh). After programming of the configuration register is finished, an additional value (AAh) should be written to EFERs to exit the Extended Function mode to prevent unintentional access to those configuration
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registers. The designer can also set bit 5 of CR26 (LOCKREG) to high to protect the configuration registers against accidental accesses. The configuration registers can be reset to their default or hardware settings only by a cold reset (pin MR = 1). A warm reset will not affect the configuration registers.
6.1.2
Extended Functions Enable Registers (EFERs)
After a power-on reset, the W83627THF enters the default operating mode. Before the W83627THF enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers. On a PC/AT system, their port addresses are 2Eh or 4Eh (as described in previous section).
6.1.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs)
After the extended function mode is entered, the Extended Function Index Register (EFIR) must be loaded with an index value (02h, 07h-FEh) to access Configuration Register 0 (CR0), Configuration Register 7 (CR07) to Configuration Register FE (CRFE), and so forth through the Extended Function Data Register (EFDR). The EFIRs are write-only registers with port address 2Eh or 4Eh (as described in section 12.2.1) on PC/AT systems, the EFDRs are read/write registers with port address 2Fh or 4Fh (as described in section 9.2.1) on PC/AT systems.
6.2
Configuration Sequence
To program W83627THF configuration registers, the following configuration sequence must be followed: (1). Enter the extended function mode (2). Configure the configuration registers (3). Exit the extended function mode
6.2.1
Enter the extended function mode
To place the chip into the extended function mode, two successive writes of 0x87 must be applied to Extended Function Enable Registers(EFERs, i.e. 2Eh or 4Eh).
6.2.2
Configuration the configuration registers
The chip selects the logical device and activates the desired logical devices through Extended Function Index Register(EFIR) and Extended Function Data Register(EFDR). EFIR is located at the same address as EFER, and EFDR is located at address (EFIR+1). First, write the Logical Device Number (i.e.,0x07) to the EFIR and then write the number of the desired logical device to the EFDR. If accessing the Chip(Global) Control Registers, this step is not required. Secondly, write the address of the desired configuration register within the logical device to the EFIR and then write (or read) the desired configuration register through EFDR.
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6.2.3 Exit the extended function mode
To exit the extended function mode, one write of 0xAA to EFER is required. Once the chip exits the extended function mode, it is in the normal running mode and is ready to enter the configuration mode.
6.2.4
Software programming example
The following example is written in Intel 8086 assembly language. It assumes that the EFER is located at 2Eh, so EFIR is located at 2Eh and EFDR is located at 2Fh. If HEFRAS (CR26 bit 6) is set, 4Eh can be directly replaced by 4Eh and 2Fh replaced by 4Fh. ;----------------------------------------------------------------------------------; Enter the extended function mode ,interruptible double-write | ;----------------------------------------------------------------------------------MOV DX,2EH MOV AL,87H OUT DX,AL OUT DX,AL ;----------------------------------------------------------------------------; Configuration logical device 1, configuration register CRF0 | ;----------------------------------------------------------------------------MOV DX,2EH MOV AL,07H OUT DX,AL ; point to Logical Device Number Reg. MOV DX,2FH MOV AL,01H OUT DX,AL ; select logical device 1 ; MOV DX,2EH MOV AL,F0H OUT DX,AL ; select CRF0 MOV DX,2FH MOV AL,3CH OUT DX,AL ; update CRF0 with value 3CH ;-----------------------------------------; Exit extended function mode | ;-----------------------------------------MOV DX,2EH MOV AL,AAH OUT DX,AL
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7. CONFIGURATION REGISTER
7.1 Chip (Global) Control Register
CR02 (Default 0x00)
Bit 7 - 1 : Reserved. Bit 0
CR07
: SWRST --> Soft Reset.
Bit 7 - 0 : LDNB7 - LDNB0 --> Logical Device Number Bit 7 - 0
CR20
Bit 7 - 0 : DEVIDB7 - DEBIDB0 --> Device ID Bit 7 - Bit 0 = 0x82(read only). CR21 Bit 7 - 0 : DEVREVB7 - DEBREVB0 --> Device Rev Bit 7 - Bit 0 = 0x83 (read only, 1 is version no.). CR22 (Default 0xff) Bit 7 Bit 6 : RESERVED. : HMPWD = 0 Power down = 1 No Power down Bit 5 : URBPWD = 0 Power down = 1 No Power down Bit 4 : URAPWD = 0 Power down = 1 No Power down Bit 3 : PRTPWD = 0 Power down = 1 No Power down Bit 2 - 1 : Reserved. Bit 0 : FDCPWD = 0 Power down = 1 No Power down
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CR23 (Default 0x00)
Bit 7 - 1 : RESERVED. Bit 0 : IPD (Immediate Power Down). down mode immediately. When set to 1, it will put the whole chip into power
CR24 (Default 0s110s1sb)
Bit 7 Bit 6
: Reserved : CLKSEL = 0 The clock input on Pin 18 should be 24 Mhz. = 1 The clock input on Pin 18 should be 48 Mhz. The corresponding power-on setting pin is SOUTB (pin 83).
Bit 5 - 3 : Reserved Bit 2 : ENKBC =0 =1 KBC is disabled after hardware reset. KBC is enabled after hardware reset.
This bit is read only, and set/reset by power-on setting pin. The corresponding poweron setting pin is SOUTA (pin 54). Bit 1 Bit 0 : Reserved. Must be 1. : PNPCSV =0 =1 The Compatible PnP address select registers have default values. The Compatible PnP address select registers have no default value.
When trying to make a change to this bit, new value of PNPCVS must be complementary to the old one to make an effective change. For example, the user must set PNPCSV to 0 first and then reset it to 1 to reset these PnP registers if the present value of PNPCSV is 1. The corresponding power-on setting pin is NDTRA (pin 52).
CR25 (Default 0x00)
Bit 7 - 6 : Reserved Bit 5 Bit 4 Bit 3 Bit 0 : URBTRI : URATRI : PRTTRI : FDCTRI.
Bit 2 - 1 : Reserved
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CR26 (Default 0s000000b) Bit 7 : SEL4FDD = 0 Select two FDD mode. = 1 Select four FDD mode. Bit 6 : HEFRAS These two bits define how to enable Configuration mode. The corresponding power-on setting pin is NRTSA (pin 51). HEFRAS Address and Value = 0 Write 87h to the location 2Eh twice. = 1 Write 87h to the location 4Eh twice. Bit 5 : LOCKREG = 0 Enable R/W Configuration Registers = 1 Disable R/W Configuration Registers. Bit 4 : Reserved Bit 3 : DSFDLGRQ = 0 Enable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is effective on selecting IRQ = 1 Disable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is not effective on selecting IRQ Bit 2 : DSPRLGRQ = 0 Enable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is effective on selecting IRQ = 1 Disable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is not effective on electing IRQ. Bit 1 : DSUALGRQ = 0 Enable UART A legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ. = 1 Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ. Bit 0 : DSUBLGRQ = 0 Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ = 1 Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ CR28 (Default 0x00) Bit 7 - 3 : Reserved. Bit 2 - 0 : PRTMODS2 - PRTMODS0 = 0xx Parallel Port Mode = 100 Reserved = 101 External FDC Mode = 110 Reserved = 111 External two FDC Mode
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CR29 (GPIO Group 1 multiplexed pin selection register 1. VCC powered. Default 0x00) Bit 7, 6 Port Select (select pin 121 ~ 128 as Game Port, General Purpose I/O Port 1 decoding feature. = 00 Game Port. = 01 General Purpose I/O Port 1. = 10 Reserved. = 11 Reserved. Bit 5 PIN105S. = 0 GP55 = 1 Winbond Test Mode Bit 4 XUR_SEL. It selects the function of pin 78 ~ 85. = 0 Pin 78 ~ 85 serve as URB function. = 1 Winbond Test Mode Bit 3 - 2 Reserved. Bit 1, 0 PIN120S1, PIN120S0 = 00 MSO (MIDI Serial Output). = 01 GP20 = 10 Reserved = 11 IRQIN0 (select IRQ resource through CRF4 Bit 7-4 of Logical Device 8). CR2A (GPIO2 multiplexed pin selection register. VCC powered. Default 0x00) Bit 7, 6 PIN119S1, PIN119S0. = 00 MSI. = 01 GP21. = 10 Winbond Test Mode = 11 Reserved. Bit 5 PIN118S. = 0 GP22. = 1 Winbond Test Mode Bit 4 PIN96S. = 0 GP23. = 1 Winbond Test Mode . Bit 3 PIN95S. = 0 GP24. = 1 Winbond Test Mode Bit 2 PIN94S. = 0 GP25. = 1 Winbond Test Mode. Bit 1 PIN93S. = 0 GP26. = 1 Winbond Test Mode Bit 0 PIN2S = 0 SMI#. = 1 IRQIN1 (select IRQ resource through CRF4 Bit 7-4 of Logical Device8).
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CR2B (GPIO3 multiplexed pin selection register 3. VSB powered. Default 0x00ssssssb) Bit 7 Reserved Bit 6 PIN86S. = 0 GP35. = 1 Winbond Test Mode Bit 5, 4 PIN88S1, PIN88S0. = 00 IRRX. = 01 GP34. = 10 Winbond Test Mode = 11 Reserved Bit 3, 2 PIN89S1, PIN89S0. = 00 GP33. = 01 WDTO. = 10 Reserved = 11 Reserved Bit 1, 0 PIN90S1, PIN90S0. = 00 GP32. = 01 PLED. = 10 Reserved. = 11 Reserved. CR2C (GPIO3 multiplexed pin selection register 2. VSB powered. Default 0xssssss00b)
Bit 7, 6
Bit 5, 4
Bit 3, 2
Bit 1
Bit 0
: PIN91S1, PIN91S0. = 00 GP31. = 01 Reserved. = 10 Reserved. = 11 Reserved : PIN92S1, PIN92S0. = 00 GP30. = 01 Reserved. = 10 Reserved. = 11 Reserved : PIN64S1, PIN64S0. = 00 SUSLED. = 01 GP37. = 10 Reserved. = 11 Reserved. : PIN87S. = 0 IRTX. = 1 Winbond Test Mode. : Reserved.
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CR2D (GPIO4 multiplexed pin selection register. VSB powered. Default 0x00s00000b) Bit 7 : PIN67S. = 0 PSOUT#. = 1 GP47. Bit 6 : PIN68S. = 0 PSIN. = 1 GP46. Bit 5 : PIN69S. = 0 GP45. = 1 Reserved. Bit 4 : PIN70S. = 0 RSMRST#. = 1 GP44. Bit 3 : PIN71S. = 0 PWROK. = 1 GP43. Bit 2 : PIN72S. = 0 PWRCTL#. = 1 GP42. Bit 1 : PIN73S. = 0 SLP_SX#. = 1 GP41. Bit 0 : PIN75S. = 0 GP40 = 1 Winbond Test Mode CR2E (Default 0x00)
Test Modes: Reserved for Winbond.
CR2F (Default 0x00)
Test Modes: Reserved for Winbond.
7.1.1
Logical Device 0 (FDC)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 1 : Reserved. Bit 0 = 1 Activates the logical device. = 0 Logical device is inactive.
CR60, CR 61 (Default 0x03, 0xf0 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise)
These two registers select FDC I/O base address [0x100:0xFF8] on 8 byte boundary.
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CR70 (Default 0x06 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 4 : Reserved. Bit 3 - 0 : These bits select IRQ resource for FDC.
CR74 (Default 0x02 if PNPCSV = 0 during POR, default 0x04 otherwise) Bit 7 - 3 : Reserved. Bit 2 - 0 : These bits select DRQ resource for FDC. = 0x00 DMA0 = 0x01 DMA1 = 0x02 DMA2 = 0x03 DMA3 = 0x04 - 0x07 No DMA active CRF0 (Default 0x0E) FDD Mode Register Bit 7 : FIPURDWN This bit controls the internal pull-up resistors of the FDC input pins RDATA, INDEX, TRAK0, DSKCHG, and WP. = 0 The internal pull-up resistors of FDC are turned on.(Default) = 1 The internal pull-up resistors of FDC are turned off. Bit 6 : INTVERTZ This bit determines the polarity of all FDD interface signals. = 0 FDD interface signals are active low. = 1 FDD interface signals are active high. Bit 5 : DRV2EN (PS2 mode only) When this bit is a logic 0, indicates a second drive is installed and is reflected in status register A. Bit 4 : Swap Drive 0, 1 Mode = 0 No Swap (Default) = 1 Drive and Motor select 0 and 1 are swapped. Bit 3 - 2 :Interface Mode = 11 AT Mode (Default) = 10 (Reserved) = 01 PS/2 = 00 Model 30 Bit 1 : FDC DMA Mode = 0 Burst Mode is enabled = 1 Non-Burst Mode (Default) Bit 0 : Floppy Mode = 0 Normal Floppy Mode (Default) = 1 Enhanced 3-mode FDD
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CRF1 (Default 0x00) Bit 7 - 6 : Boot Floppy = 00 FDD A = 01 FDD B = 10 FDD C = 11 FDD D Bit 5, 4 : Media ID1, Media ID0. These bits will be reflected on FDC's Tape Drive Register bit 7, 6. Bit 3 - 2 : Density Select = 00 Normal (Default) = 01 Normal = 10 1 (Forced to logic 1) = 11 0 (Forced to logic 0) Bit 1 : DISFDDWR = 0 Enable FDD write. = 1 Disable FDD write(forces pins WE, WD stay high). Bit 0 : SWWP = 0 Normal, use WP to determine whether the FDD is write protected or not. = 1 FDD is always write-protected. CRF2 (Default 0xFF)
Bit 7 - 6 : FDD D Drive Type Bit 5 - 4 : FDD C Drive Type Bit 3 - 2 : FDD B Drive Type Bit 1 - 0 : FDD A Drive Type
CRF4 (Default 0x00) FDD0 Selection: Bit 7 : Reserved. Bit 6 : Pre-comp. Disable. = 1 Disable FDC Pre-compensation. = 0 Enable FDC Pre-compensation. Bit 5 : Reserved. Bit 4 - 3 : DRTS1, DRTS0: Data Rate Table select (Refer to TABLE A). = 00 Select Regular drives and 2.88 format = 01 3-mode drive = 10 2 Meg Tape = 11 Reserved Bit 2 : Reserved. Bit 1:0 : DTYPE0, DTYPE1: Drive Type select (Refer to TABLE B).
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CRF5 (Default 0x00)
FDD1 Selection: Same as FDD0 of CRF4.
TABLE A
DRIVE RATE TABLE SELECT DRTS1 DRTS0 DATA RATE DRATE1 DRATE0 SELECTED DATA RATE MFM FM SELDEN
1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1
1 0 1 0 1 0 1 0 1 0 1 0
1Meg 500K 300K 250K 1Meg 500K 500K 250K 1Meg 500K 2Meg 250K
--250K 150K 125K --250K 250K 125K --250K --125K
1 1 0 0 1 1 0 0 1 1 0 0
TABLE B
DTYPE0 DTYPE1 DRVDEN0(PIN 2) DRVDEN1(PIN 3) DRIVE TYPE
4/2/1 MB 3.5"" 0 0 1 1 0 1 0 1 SELDEN DRATE1
SELDEN
DRATE0 DRATE0 DRATE0 DRATE1
2/1 MB 5.25" 2/1.6/1 MB 3.5" (3-MODE)
DRATE0
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7.1.2
Logical Device 1 (Parallel Port)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 1 : Reserved. Bit 0 = 1 Activates the logical device. = 0 Logical device is inactive.
CR60, CR 61 (Default 0x03, 0x78 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise)
These two registers select Parallel Port I/O base address. [0x100:0xFFC] on 4 byte boundary (EPP not supported) or [0x100:0xFF8] on 8 byte boundary (All modes supported, EPP is only available when the base address is on 8 byte boundary).
CR70 (Default 0x07 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 4 : Reserved. Bit [3:0] : These bits select IRQ resource for Parallel Port.
CR74 (Default 0x04)
Bit 7 - 3 : Reserved. Bit 2 - 0 : These bits select DRQ resource for Parallel Port. 0x00 = DMA0 0x01 = DMA1 0x02 = DMA2 0x03 = DMA3 0x04 - 0x07 = No DMA active
CRF0 (Default 0x3F) Bit 7 : Reserved. Bit 6 - 3 : ECP FIFO Threshold. Bit 2 - 0 : Parallel Port Mode (CR28 PRTMODS2 = 0) = 100 Printer Mode (Default) = 000 Standard and Bi-direction (SPP) mode = 001 EPP - 1.9 and SPP mode = 101 EPP - 1.7 and SPP mode = 010 ECP mode = 011 ECP and EPP - 1.9 mode = 111 ECP and EPP - 1.7 mode.
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7.1.3 Logical Device 2 (UART A)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 1 : Reserved. Bit 0 = 1 Activates the logical device. = 0 Logical device is inactive.
CR60, CR 61 (Default 0x03, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise)
These two registers select Serial Port 1 I/O base address [0x100:0xFF8] on 8 byte boundary.
CR70 (Default 0x04 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 4 : Reserved. Bit 3 - 0 : These bits select IRQ resource for Serial Port 1.
CRF0 (Default 0x00)
Bit 7 - 2 : Reserved. Bit 1 - 0 : SUACLKB1, SUACLKB0 = 00 UART A clock source is 1.8462 Mhz (24MHz/13) = 01 UART A clock source is 2 Mhz (24MHz/12) = 10 UART A clock source is 24 Mhz (24MHz/1) = 11 UART A clock source is 14.769 Mhz (24mhz/1.625)
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7.1.4 Logical Device 3 (UART B)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 1 : Reserved. Bit 0 = 1 Activates the logical device. = 0 Logical device is inactive.
CR60, CR 61 (Default 0x02, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise)
These two registers select Serial Port 2 I/O base address [0x100:0xFF8] on 8 byte boundary.
CR70 (Default 0x03 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 4 : Reserved. Bit [3:0] : These bits select IRQ resource for Serial Port 2.
CRF0 (Default 0x00) Bit 7 - 4 : Reserved. Bit 3 : RXW4C = 0 No reception delay when SIR is changed from TX mode to RX mode. = 1 Reception delays 4 characters - time (40 bit-time) when SIR is changed from TX mode to RX mode. Bit 2 : TXW4C = 0 No transmission delay when SIR is changed from RX mode to TX mode. = 1Transmission delays 4 characters-time (40 bit-time) when SIR is changed from RX mode to TX mode. Bit 1 - 0 : SUBCLKB1, SUBCLKB0 = 00 UART B clock source is 1.8462 Mhz (24MHz/13) = 01 UART B clock source is 2 Mhz (24MHz/12) = 10 UART B clock source is 24 Mhz (24MHz/1) = 11 UART B clock source is 14.769 Mhz (24mhz/1.625) CRF1 (Default 0x00)
Bit 7 Bit 6
: Reserved. : IRLOCSEL. IR I/O pins' location select. = 0 Through SINB/SOUTB. = 1 Through IRRX/IRTX.
Bit 5 Bit 4 Bit 3
: IRMODE2. IR function mode selection bit 2. : IRMODE1. IR function mode selection bit 1. : IRMODE0. IR function mode selection bit 0.
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IR MODE IR FUNCTION IRTX IRRX
00X 010* 011* 100 101 110 111*
Disable IrDA IrDA ASK-IR ASK-IR ASK-IR ASK-IR
tri-state Active pulse 1.6 S Active pulse 3/16 bit time Inverting IRTX/SOUTB pin Inverting IRTX/SOUTB & 500 KHZ clock Inverting IRTX/SOUTB Inverting IRTX/SOUTB & 500 KHZ clock
high Demodulation into SINB/IRRX Demodulation into SINB/IRRX routed to SINB/IRRX routed to SINB/IRRX Demodulation into SINB/IRRX Demodulation into SINB/IRRX
Note: The notation is normal mode in the IR function.
Bit 2
: HDUPLX. IR half/full duplex function select. = 0 The IR function is Full Duplex. = 1 The IR function is Half Duplex.
Bit 1
: TX2INV = 0 The SOUTB pin of UART B function or IRTX pin of IR function in normal condition. = 1 Inverse the SOUTB pin of UART B function or IRTX pin of IR function.
Bit 0
: RX2INV. = 0 The SINB pin of UART B function or IRRX pin of IR function in normal condition. = 1 Inverse the SINB pin of UART B function or IRRX pin of IR function
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7.1.5 Logical Device 5 (KBC)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 1 : Reserved. Bit 0 = 1 Activates the logical device. = 0 Logical device is inactive.
CR60, CR 61 (Default 0x00, 0x60 if PNPCSV = 0 during POR, default 0x00 otherwise)
These two registers select the first KBC I/O base address [0x100:0xFFF] on 1 byte boundary.
CR62, CR 63 (Default 0x00, 0x64 if PNPCSV = 0 during POR, default 0x00 otherwise)
These two registers select the second KBC I/O base address [0x100:0xFFF] on 1 byte boundary.
CR70 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 4 : Reserved. Bit [3:0] : These bits select IRQ resource for KINT (keyboard).
CR72 (Default 0x0C if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 4 : Reserved. Bit [3:0] : These bits select IRQ resource for MINT (PS2 Mouse)
CRF0 (Default 0x80)
Bit 7 - 6 : KBC clock rate selection = 00 Select 6MHz as KBC clock input. = 01 Select 8MHz as KBC clock input. = 10 Select 12Mhz as KBC clock input. = 11 Select 16Mhz as KBC clock input. Bit 5 - 3 : Reserved. Bit 2 Bit 1 Bit 0 = 0 Port 92 disable. = 1 Port 92 enable. = 0 Gate20 software control. = 1 Gate20 hardware speed up. = 0 KBRST software control. = 1 KBRST hardware speed up.
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7.1.6 Logical Device 7 (Game Port and MIDI Port and GPIO Port 1 and 5)
CR30 (Default 0x00)
Bit 7 - 4 : Reserved. Bit 3 Bit 2 Bit 1 Bit 0 = 1 Enable GPIO port 5. = 0 Disable GPIO port 5. = 1 Enable MIDI Port. = 0 MIDI Port is disabled if bit 0 of this register is also 0. = 1 Enable game Port. = 0 Game Port is disabled if bit 0 of this register is also 0. = 1 Enable GPIO port 1, game Port and MIDI Port. = 0 Disable GPIO port 1. Game Port and MIDI Port are enabled/disabled by bit 1 and 2 of this register respectively.
CR60, CR 61 (Default 0x02, 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)
These two registers select the Game Port base address [0x100:0xFFF] on 1 byte boundary.
CR62, CR 63 (Default 0x03, 0x30 if PNPCSV = 0 during POR, default 0x00 otherwise)
These two registers select the MIDI Port base address [0x100:0xFFF] on 2 byte boundary.
CR70 (Default 0x09 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 4 : Reserved. Bit [3:0] : These bits select IRQ resource for MIDI Port .
CRF0 (GP1[7:0] I/O selection register. Default 0xFF)
When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port.
CRF1 (GP1[7:0] data register. Default 0x00)
If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read.
CRF2 (GP1[7:0] inversion register. Default 0x00)
When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register.
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CRF3 (GP5[5:0] I/O selection register. Default 0xFF)
When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port.
CRF4 (GP5[5:0] data register. Default 0x00)
If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read.
CRF5 (GP5[5:0] inversion register. Default 0x00)
When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register.
7.1.7
Logical Device 8 (GPIO Port 2 This power of the Port is VCC source)
CR30 (GP2[7:0] Default 0x00)
Bit 7 - 1 : Reserved. Bit 0 = 1 Activate GPIO2. = 0 GPIO2 is inactive.
CRF0 (GP2[7:0] I/O selection register. Default 0xFF)
When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port.
CRF1 (GP2[7:0] data register. Default 0x00)
If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read.
CRF2 (GP2[7:0] inversion register. Default 0x00)
When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register.
CRF3 (Default 0x00)
Bit 7 - 4 : These bits select IRQ resource for IRQIN1. Bit 3 - 0 : These bits select IRQ resource for IRQIN0.
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CRF4 (Reserved) CRF5 (PLED mode register. Default 0x00) Bit 7-6 : Select PLED mode = 00 Power LED pin is tri-stated. = 01 Power LED pin is driven low. = 10 Power LED pin is a 1Hz toggle pulse with 50 duty cycle = 11 Power LED pin is a 1/4Hz toggle pulse with 50 duty cycle. Bit 5-4 : Reserved Bit 3 : Select WDTO counter type. = 0 By second = 1 By minute Bit 2 : Enable the rising edge of keyboard Reset (P20) to force Time-out event. = 0 Disable = 1 Enable Bit 1-0 : Reserved CRF6 (Default 0x00)
Watch Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to load the value to Watch Dog Counter and start counting down. If the Bit 7 and Bit 6 are set, any Mouse Interrupt or Keyboard Interrupt event will also cause the reload of previously-loaded non-zero value to Watch Dog Counter and start counting down. Reading this register returns current value in Watch Dog Counter instead of Watch Dog Timer Time-out value. Bit 7 - 0 = 0x00 Time-out Disable = 0x01 Time-out occurs after 1 second/minute = 0x02 Time-out occurs after 2 second/minutes = 0x03 Time-out occurs after 3 second/minutes ................................................ = 0xFF Time-out occurs after 255 second/minutes CRF7 (Default 0x00) Bit 7 : Mouse interrupt reset Enable or Disable = 1 Watch Dog Timer is reset upon a Mouse interrupt = 0 Watch Dog Timer is not affected by Mouse interrupt Bit 6 : Keyboard interrupt reset Enable or Disable = 1 Watch Dog Timer is reset upon a Keyboard interrupt = 0 Watch Dog Timer is not affected by Keyboard interrupt Bit 5 : Force Watch Dog Timer Time-out, Write only* = 1 Force Watch Dog Timer time-out event; this bit is self-clearing. Bit 4 : Watch Dog Timer Status, R/W = 1 Watch Dog Timer time-out occurred = 0 Watch Dog Timer counting Bit 3 -0 : These bits select IRQ resource for Watch Dog. Setting of 2 selects SMI.
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7.1.8 Logical Device 9 (GPIO Port 3, 4. These two ports are powered by VSB)
CR30 (Default 0x00) Bit 7 - 2 : Reserved Bit 1 = 1 Activate GPIO4. = 0 GPIO4 is inactive. Bit 0 = 1 Activate GPIO3. = 0 GPIO3 is inactive. CRF0 (GP3[7:0] I/O selection register. Default 0xFF)
When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port.
CRF1 (GP3[7:0] data register. Default 0x00)
If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read.
CRF2 (GP3[7:0] inversion register. Default 0x00)
When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register.
CRF3 (SUSLED mode register. Default 0x00)
Bit 7-6
: Select Suspend LED mode = 00 Suspend LED pin is drove low. = 01 Suspend LED pin is tri-stated. = 10 Suspend LED pin is a 1Hz toggle pulse with 50 duty cycle. = 11 Suspend LED pin is a 1/4Hz toggle pulse with 50 duty cycle.
This mode selection bit 7-6 keep its settings until VSB power loss. Bit 5 - 0 : Reserved.
CRF4 (GP4[7:0] I/O selection register. Default 0xFF)
When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port.
CRF5 (GP4[7:0] data register. Default 0x00)
If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read.
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W83627THF/W83627THG
CRF6 (GP4[7:0] inversion register. Default 0x00)
When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register.
7.2
Logical Device A (ACPI)
(The CR30,70,F0~F9 are VCC power source; CR E0~E7 are VRTC power source)
CR30 (Default 0x00)
Bit 7 - 1 : Reserved. Bit 0 = 1 Activates the logical device. = 0 Logical device is inactive.
CR70 (Default 0x00)
Bit 7 - 4 : Reserved. Bit 3 - 0 : These bits select IRQ resources for PME .
CRE0 (Default 0x00) Bit 7 : DIS-PANSW_IN. Disable panel switch input to turn system power supply on. = 0 PANSW_IN is wire-ANDed and connected to PANSW_OUT. = 1 PANSW_IN is blocked and can not affect PANSW_OUT. Bit 6 : ENKBWAKEUP. Enable Keyboard to wake-up system via PANSW_OUT. = 0 Disable Keyboard wake-up function. = 1 Enable Keyboard wake-up function. Bit 5 : ENMSWAKEUP. Enable Mouse to wake-up system via PANSW_OUT. = 0 Disable Mouse wake-up function. = 1 Enable Mouse wake-up function. Bit 4 : MSRKEY. This bit combining with MSXKEY (bit 1 of CRE0 of logical device A) and ENMDAT_UP (bit 7 of CRE6 of logical device A) define what kind of mouse wake-up event can trigger an active low pulse on PSOUT#. Their combination is described in the following table. ENMDAT_UP 1 1 0 0 0 0 MSRKEY x x 0 1 0 1 MSXKEY 1 0 1 1 0 0 WAKE UP EVENT Any button click or any movement one click of left/right button one click of left button one click of right button two times click of left button two times click of right button
Bit 3 Bit 2
Reserved : KB/MS Swap. Enable Keyboard/Mouse port-swap. = 0 Keyboard/Mouse ports are not swapped. = 1 Keyboard/Mouse ports are swapped.
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W83627THF/W83627THG
Bit 1 : MSXKEY. This bit combining with MSRKEY (bit 4 of CRE0 of logical device A) and ENMDAT_UP (bit 7 of CRE6 of logical device A) define what kind of mouse wake-up event can trigger an active low pulse on PSOUT#. Their combination is described in the following table.
ENMDAT_UP 1 1 0 0 0 0 MSRKEY x x 0 1 0 1 MSXKEY 1 0 1 1 0 0 WAKE UP EVENT Any button click or any movement one click of left/right button one click of left button one click of right button two times click of left button two times click of right button
Bit 0
: KBXKEY. Enable any character received from Keyboard to wake-up the system =0 Only predetermined specific key combination can wake up the system. =1 Any character received from Keyboard can wake up the system.
CRE1 (Default 0x00) Keyboard Wake-Up Index Register
This register is used to indicate which Keyboard Wake-Up Shift register or Predetermined key Register is to be read/written via CRE2. The first set of wake up key combination is in the range of 0x00 - 0x0E, the second set 0x30 - 0x3E, and the third set 0x40 - 0x4E. Incoming key combination can be read through 0x10 - 0x1E.
CRE2 Keyboard Wake-Up Data Register
This register holds the value of wake-up key register indicated by CRE1. This register can be read/written.
CRE3 (Read only) Keyboard/Mouse Wake-Up Status Register
Bit 7-5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
: Reserved. : PWRLOSS_STS: This bit is set when power loss occurs. Reserved : PANSW_STS. The Panel switch event is caused by PANSW_IN. This bit is cleared by reading this register. : Mouse_STS. The Panel switch event is caused by Mouse wake-up event. cleared by reading this register. This bit is
: Keyboard_STS. The Panel switch event is caused by Keyboard wake-up event. This bit is cleared by reading this register.
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W83627THF/W83627THG
CRE4 (Default 0x00) Bit 7 : Power loss control bit 2. = 0 Disable ACPI resume = 1 Enable ACPI resume Bit 6-5 : Power loss control bit <1:0> = 00 System always turn off when come back from power loss state. = 01 System always turn on when come back from power loss state. = 10 System turn on/off when come back from power loss state depend on the state before power loss. = 11 Reserved. Bit 4 : Reserved Bit 3 : Keyboard wake-up type select for wake-up the system from S1/S2. = 0 LA.CRE0.bit0 determines how system wake up from S1/S2. = 1 Any key. Bit 2 : Enable all wake-up event set in CRE0 can wake-up the system from S1/S2 state. This bit is cleared when wake-up event occurs. = 0 Disable. = 1 Enable. Bit 1 - 0 : Reserved. Must be 00b. CRE5 (Default 0x00)
Bit 7
: Reserved.
Bit 6 - 0 : Compared Code Length. When the compared codes are storied in the data register, these data length should be written to this register.
CRE6 (Default 0x00)
Bit 7
ENMDAT_UP. This bit combining with MSRKEY (bit 4 of CRE0 of logical device A) and MSXKEY (bit 1 of CRE0 of logical device A) define what kind of mouse wake-up event can trigger an active low pulse on PSOUT#. Their combination is described in the following table.
ENMDAT_UP 1 1 0 0 0 0 MSRKEY x x 0 1 0 1 MSXKEY 1 0 1 1 0 0 WAKE UP EVENT Any button click or any movement one click of left/right button one click of left button one click of right button two times click of left button two times click of right button
Bit6
Chassis Status Clear = 1 Clear CASEOPEN# (Pin76) event. = 0 Disable Clear Function.
Bit 5 - 0 Reserved
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CRE7 (Default 0x00)
Bit 7
ENKD3. Enable the third set of keyboard wake-up key combinations. Its values are accessed through keyboard wake-up index register (CRE1 of logical device A) and keyboard wake-up data register (CRE2 of logical device A) at index from 40h to 4eh. = 0 disable wake-up function of the third set of key combinations. = 1 enable wake-up function of the third set of key combinations.
Bit 6
ENKD2. Enable the second set of keyboard wake-up key combinations. Its values are accessed through keyboard wake-up index register (CRE1 of logical device A) and keyboard wake-up data register (CRE2 of logical device A) at index from 30h to 3eh. = 0 disable wake-up function of the second set of key combinations. = 1 enable wake-up function of the second set of key combinations.
Bit 5
ENWIN98KEY. Enable WIN98 keyboard dedicated key to wake up system through PANSW_OUT if keyboard wake up function is enabled. = 0 Disable WIN98 keyboard wake up. = 1 Enable WIN98 keyboard wake up.
Bit 4
EN_ONPSOUT. Enable to issue a 0.5s long PSOUT# pulse when system returns from power loss state and is supposed to be on as described in CRE4 bit 6, 5 of logical device A. = 0 Disable this function for Intel's Chipset. = 1 Enable this function for Clone's chipset.
Bit 3
SELWDTORST: Select whether Watch Dog timer function is reset by LRESET_L signal or PWROK signal. =0 Watch Dog timer function is reset by LRESET_L signal. =1 Watch Dog timer function is reset by PWROK signal.
Bit 2 Bit 1 Bit 0
Reserved Reserved Reserved
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W83627THF/W83627THG
CRF0 (Default 0x00)
Bit 7
: CHIPPME. Chip level auto power management enable. = 0 disable the auto power management functions = 1 enable the auto power management functions.
Bit 6 Bit 5
Reserved : MIDIPME. MIDI port auto power management enable. = 0 disable the auto power management functions = 1 enable the auto power management functions.
Bit 4 Bit 3
: Reserved. Return zero when read. : PRTPME. Printer port auto power management enable. = 0 disable the auto power management functions. = 1 enable the auto power management functions.
Bit 2
: FDCPME. FDC auto power management enable. = 0 disable the auto power management functions. = 1 enable the auto power management functions.
Bit 1
: URAPME. UART A auto power management enable. = 0 disable the auto power management functions. = 1 enable the auto power management functions.
Bit 0
: URBPME. UART B auto power management enable. = 0 disable the auto power management functions. = 1 enable the auto power management functions.
CRF1 (Default 0x00)
Bit 7
: WAK_STS. This bit is set when the chip is in the sleeping state and an enabled resume event occurs. Upon setting this bit, the sleeping/working state machine will transition the system to the working state. This bit is only set by hardware and is cleared by writing a 1 to this bit position or by the sleeping/working state machine automatically when the global standby timer expires. = 0 the chip is in the sleeping state. = 1 the chip is in the working state.
Bit 6 - 5 : Devices' trap status. Bit 4 : Reserved. Return zero when read. Bit 3 - 0 : Devices' trap status.
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CRF3 (Default 0x00)
Bit 7 - 0 : Device's IRQ status. These bits indicate the IRQ status of the individual device respectively. The device's IRQ status bit is set by their source device and is cleared by writing a 1. Writing a 0 has no effect. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 : Reserved. : Reserved. : MOUIRQSTS. MOUSE IRQ status. : KBCIRQSTS. KBC IRQ status. : PRTIRQSTS. printer port IRQ status. : FDCIRQSTS. FDC IRQ status. : URAIRQSTS. UART A IRQ status. : URBIRQSTS. UART B IRQ status.
CRF4 (Default 0x00)
Bit 7
: Reserved. Return zero when read.
Bit 6 - 0 : These bits indicate the IRQ status of the individual GPIO function or logical device respectively. The status bit is set by their source function or device and is cleared by writing a1. Writing a 0 has no effect. Bit 6 Bit 5 Bit 4 Bit 3 Bit 1 Bit 0 :Reserved : HMIRQSTS. Hardware monitor IRQ status. : WDTIRQSTS. Watch dog timer IRQ status. Reserved : IRQIN1STS. IRQIN1 status. : IRQIN0STS. IRQIN0 status.
CRF6 (Default 0x00)
Bit 7 - 0 : Enable bits of the SMI / PME generation due to the device's IRQ. These bits enable the generation of an SMI / PME interrupt due to any IRQ of the devices. SMI / PME logic output = (MOUIRQEN and MOUIRQSTS) or (KBCIRQEN and KBCIRQSTS) or (PRTIRQEN and PRTIRQSTS) or (FDCIRQEN and FDCIRQSTS) or (URAIRQEN and URAIRQSTS) or (URBIRQEN and URBIRQSTS) or (HMIRQEN and HMIRQSTS) or (WDTIRQEN and WDTIRQSTS) or (IRQIN3EN and IRQIN3STS) or (IRQIN2EN and IRQIN2STS) or (IRQIN1EN and IRQIN1STS) or (IRQIN0EN and IRQIN0STS) Bit 7 Bit 6 Reserved. Reserved
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Bit 5 : MOUIRQEN. = 0 disable the generation of an SMI / PME interrupt due to MOUSE's IRQ. Bit 4 = 1 enable the generation of an SMI / PME interrupt due to MOUSE's IRQ. : KBCIRQEN. = 0 disable the generation of an SMI / PME interrupt due to KBC's IRQ. Bit 3 = 1 enable the generation of an SMI / PME interrupt due to KBC's IRQ. : PRTIRQEN. = 0 disable the generation of an SMI / PME interrupt due to printer port's IRQ. Bit 2 = 1 enable the generation of an SMI / PME interrupt due to printer port's IRQ. : FDCIRQEN. = 0 disable the generation of an SMI / PME interrupt due to FDC's IRQ. Bit 1 = 1 enable the generation of an SMI / PME interrupt due to FDC's IRQ. : URAIRQEN. = 0 disable the generation of an SMI / PME interrupt due to UART A's IRQ. Bit 0 = 1 enable the generation of an SMI / PME interrupt due to UART A's IRQ. : URBIRQEN. = 0 disable the generation of an SMI / PME interrupt due to UART B's IRQ. = 1 enable the generation of an SMI / PME interrupt due to UART B's IRQ.
CRF7 (Default 0x00) Bit 7 : Reserved. Return zero when read Bit 6 - 0 : Enable bits of the SMI / PME generation due to the GPIO IRQ function or device's IRQ.
Bit 6 Bit 5
Reserved : HMIRQEN. = 0 disable the generation of an SMI / PME interrupt due to hardware monitor's IRQ. = 1 enable the generation of an SMI / PME interrupt due to hardware monitor's IRQ. : WDTIRQEN. = 0 disable the generation of an SMI / PME interrupt due to watch dog timer's IRQ. = 1 enable the generation of an SMI / PME interrupt due to watch dog timer's IRQ. Reserved : MIDIIRQEN. = 0 disable the generation of an SMI / PME interrupt due to MIDI's IRQ. = 1 enable the generation of an SMI / PME interrupt due to MIDI's IRQ. : IRQIN1EN. = 0 disable the generation of an SMI / PME interrupt due to IRQIN1's IRQ. = 1 enable the generation of an SMI / PME interrupt due to IRQIN1's IRQ.
Bit 4
Bit 3 Bit 2
Bit 1
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Bit 0 : IRQIN0EN. = 0 disable the generation of an SMI / PME interrupt due to IRQIN0's IRQ. = 1 enable the generation of an SMI / PME interrupt due to IRQIN0's IRQ.
CRF9 (Default 0x00)
Bit 7 - 3 : Reserved. Return zero when read. Bit 2 : PME_EN: Select the power management events to be either an PME or SMI interrupt for the IRQ events. Note that: this bit is valid only when SMIPME_OE = 1. = 0 the power management events will generate an SMI event = 1 the power management events will generate an PME event. Bit 1 : FSLEEP: This bit selects the fast expiry time of individual devices. = 0 1 second. = 1 8 mS Bit 0 : SMIPME_OE: This is the SMI and PME output enable bit. = 0 neither SMI nor PME will be generated. Only the IRQ status bit is set. = 1 an SMI or PME event will be generated.
CRFE, FF (Default 0x00)
Reserved for Winbond test.
7.3
Logical Device B (Hardware Monitor)
CR30 (Default 0x00)
Bit 7 - 1 : Reserved. Bit 0 = 1 Activates the logical device. = 0 Logical device is inactive.
CR60, CR 61 (Default 0x00, 0x00)
These two registers select Hardware Monitor base address [0x100:0xFFF] on 8-byte boundary.
CR70 (Default 0x00)
Bit 7 - 4 : Reserved. Bit 3 - 0 : These bits select IRQ channel for Hardware Monitor.
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W83627THF/W83627THG
8. AC/DC SPECIFICATIONS
8.1 Absolute Maximum Ratings
PARAMETER RATING UNIT
Power Supply Voltage (5V) Input Voltage RTC Battery Voltage VBAT Operating Temperature Storage Temperature
-0.5 to 7.0 -0.5 to VDD+0.5 2.2 to 4.0 0 to +70 -55 to +150
V V V
C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
8.2
DC CHARACTERISTICS
PARAMETER SYM. MIN. TYP MAX. UNIT CONDITIONS
(Ta = 0 C to 70 C, VDD = 5V 10%, VSS = 0V) RTC Battery Quiescent Current ACPI Stand-by Power Supply Quiescent current
INcs
IBAT IBAT
2.4 2.0
uA mA
VBAT = 2.5 V VSB = 5.0 V, All ACPI pins are not connected.
- CMOS level Schmitt-triggered input pin
Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage
INt - TTL level input pin
VtVt+ VTH ILIH ILIL
1.3 3.2 1.5
1.5 3.5 2
1.7 3.8
V V V
VDD = 5 V VDD = 5 V VDD = 5 V VIN = 5 V VIN = 0 V
+10 -10
A A
Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage
VIL VIH ILIH ILIL 2.0
0.8
V V
+10 -10
A A
VIN = 5 V VIN = 0 V
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W83627THF/W83627THG
DC CHARACTERISTICS, continued.
PARAMETER
SYM.
MIN.
TYP
MAX.
UNIT
CONDITIONS
INtd - TTL level input pin with internal pull down resistor
Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage pull down resistor
INts
VIL VIH ILIH ILIL R 2.0
0.8
V V
+10 -10 47
A A
VIN = 5 V VIN = 0 V
K
- TTL level Schmitt-triggered input pin
Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage
INtsp3
VtVt+ VTH ILIH ILIL
0.8 1.8 0.8
0.9 1.9 1.0
1.0 2.0
V V V
VDD = 5 V VDD = 5 V VDD = 5 V VIN = 5 V VIN = 0 V
+10 -10
A A
- 3.3 V TTL level Schmitt-triggered input pin
Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage
VtVt+ VTH ILIH ILIL
0.5 1.6 0.5
0.8 2.0 1.2
1.1 2.4
V V V
VDD = 3.3 V VDD = 3.3 V VDD = 3.3 V VIN = 3.3 V VIN = 0 V
+10 -10
A A
INtu - TTL level input pin with internal pull up resistor
Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage pull up resistor
VIL VIH ILIH ILIL R 40 2.0
0.8
V V
+10 -10
A A
VIN = 5 V VIN = 0 V
K
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W83627THF/W83627THG
DC CHARACTERISTICS, continued.
PARAMETER
SYM.
MIN.
TYP
MAX.
UNIT
CONDITIONS
I/O8t - TTL level bi-directional pin with source-sink capability of 8 mA
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage
VIL VIH VOL VOH ILIH ILIL VIL VIH VOL VOH ILIH ILIL VIL VIH VOL VOH ILIH ILIL 2.4 2.0 2.4 2.0 2.4 2.0
0.8 0.4 +10 -10
V V V V
A A
IOL = 8 mA IOH = - 8 mA VIN = 5 V VIN = 0 V
I/O12t - TTL level bi-directional pin with source-sink capability of 12 mA
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage
0.8 0.4 +10 -10
V V V V
A A
IOL = 12 mA IOH = -12 mA VIN = 5 V VIN = 0 V
I/O12tp3 - 3.3 V TTL level bi-directional pin with source-sink capability of 12 mA
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage
0.8
V V
0.4
V V
A A
IOL = 12 mA IOH = -12 mA VIN = 3.3 V VIN = 0 V
+10 -10
I/OD12ts - TTL level bi-directional Schmitt-triggered pin. Open-drain output with 12 mA sink capability
Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage
VtVt+ VTH VOL ILIH ILIL
0.8 1.8 0.8
0.9 1.9 1.0
1.0 2.0
V V V
VDD = 5 V VDD = 5 V VDD = 5 V IOL = 12 mA VIN = 5 V VIN = 0 V
0.4 +10 -10
V
A A
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W83627THF/W83627THG
DC CHARACTERISTICS, continued.
PARAMETER
SYM.
MIN.
TYP
MAX.
UNIT
CONDITIONS
I/OD12tp3 - 3.3 V TTL level bi-directional pin. Open-drain output with 12 mA sink capability
Input Low Voltage Input High Voltage Output Low Voltage Input High Leakage Input Low Leakage
VIL VIH VOL ILIH ILIL 2.0
0.8
V V
0.4 +10 -10
V
A A
IOL = 12 mA VIN = 3.3V VIN = 0V
I/OD16cs - CMOS level Schmitt-triggered bi-directional pin. Open-drain output with 16 mA sink capability
Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input Low Voltage Input High Voltage Output Low Voltage Input High Leakage Input Low Leakage
VtVt+ VTH VIL VIH VOL ILIH ILIL VIL VIH VOL ILIH ILIL VOL VOL VOL
1.3 3.2 1.5
1.5 3.5 2
1.7 3.8
V V V
VDD = 5 V VDD = 5 V VDD = 5 V
0.8 2.0 0.4 +10 -10
V V V
A A
IOL = 16 mA VIN = 5 V VIN = 0 V
I/OD24t - TTL level bi-directional pin.
Open-drain output with 24 mA sink capability
Input Low Voltage Input High Voltage Output Low Voltage Input High Leakage Input Low Leakage Output Low Voltage Output Low Voltage Output Low Voltage
0.8 2.0 0.4 +10 -10 0.4 0.4 0.4
V V V
A A
IOL = 24 mA VIN = 5 V VIN = 0 V IOL = 8 mA IOL = 12 mA IOL = 24 mA
OD8 - Open-drain output pin with sink capability of 8 mA
V V V
OD12 - Open-drain output pin with sink capability of 12 mA OD24 - Open-drain output pin with sink capability of 24 mA
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W83627THF/W83627THG
DC CHARACTERISTICS, continued.
PARAMETER
SYM.
MIN.
TYP
MAX.
UNIT
CONDITIONS
OUT8 - TTL level output pin with source-sink capability of 8 mA
Output Low Voltage Output High Voltage
VOL VOH VOL VOH VOL VOH VOL VOH 2.4 2.4 2.4 2.4
0.4
V V
IOL = 8 mA IOH = -8 mA IOL = 12 mA IOH = -12 mA IOL = 24 mA IOH = -24 mA IOL = 12 mA IOH = -12 mA
OUT12 - TTL level output pin with source-sink capability of 12 mA
Output Low Voltage Output High Voltage
0.4
V V
OUT24 - TTL level output pin with source-sink capability of 24 mA
Output Low Voltage Output High Voltage
0.4
V V
OUT12tp3 - 3.3 V TTL level output pin with source-sink capability of 12 mA
Output Low Voltage Output High Voltage
0.4
V V
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9. APPLICATION CIRCUITS
9.1 Parallel Port Extension FDD
JP13
WE2/SLCT WD2/PE MOB2/BUSY DSB2/ACK PD7 PD6 PD5 DCH2/PD4 RDD2/PD3 STEP2/SLIN WP2/PD2 DIR2/INIT TRK02/PD1 HEAD2/ERR IDX2/PD0 RWC2/AFD STB 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1
JP 13A
DCH2 HEAD2 RDD2
WP2
TRK02 WE2 WD2 STEP2 DIR2 MOB2 DSB2 IDX2
RWC2
34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
EXT FDC
PRINTER PORT
Parallel Port Extension FDD Mode Connection Diagram
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W83627THF/W83627THG
9.2 Parallel Port Extension 2FDD
JP13
WE2/SLCT WD2/PE MOB2/BUSY DSB2/ACK DSA2/PD7 MOA2/PD6 PD5 DCH2/PD4 RDD2/PD3 STEP2/SLIN WP2/PD2 DIR2/INIT TRK02/PD1 HEAD2/ERR IDX2/PD0 RWC2/AFD STB 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1
JP 13A
DCH2 HEAD2 RDD2
WP2
TRK02 WE2 WD2 STEP2 DIR2 MOB2 DSA2 DSB2 MOA2 IDX2
RWC2
34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
EXT FDC
PRINTER PORT
Parallel Port Extension 2FDD Connection Diagram
9.3
Four FDD Mode
74LS139 W83977F DSA DSB MOA MOB G2 A2 B2 G1 A1 B1 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3
7407(2) DSA DSB DSC DSD MOA MOB MOC MOD
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W83627THF/W83627THG
10. HOW TO READ THE TOP MARKING
Example: The top marking of W83627THF,W83627THG
inbond
W83627THF
030A7C282012345UA
inbond
W83627THG
030A7C282012345UA
1st line: Winbond logo 2nd line: the type number: W83627THF, W83627THG the "G" means Pb-free package 3rd line: the tracking code 030A7C282012345UA 030: packages made in '00, week 30 A: assembly house ID; A means ASE, S means SPIL.... etc. 7: code version; 7 means code 007 C: IC revision; A means version A, B means version B 282012345: wafer production series lot number UA: Winbond internal use.
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W83627THF/W83627THG
11. PACKAGE DIMENSIONS
(128-pin QFP)
HE E
102 65
Symbol Min
Dimension in mm
Dimension in inch
Nom
0.35 2.72 0.20 0.15 14.00 20.00 0.50
Max
0.45 2.87 0.30 0.20 14.10 20.10
Min
0.010 0.101 0.004 0.004 0.547 0.783
Nom
0.014 0.107 0.008 0.006 0.551 0.787 0.020
Max
0.018 0.113 0.012 0.008 0.555 0.791
103
64
D
HD
128
39
1
e
b
38
A1 A2 b c D E e HD HE L L1 y 0
c
0.25 2.57 0.10 0.10 13.90 19.90
17.00 23.00 0.65
17.20 23.20 0.80 1.60
17.40 23.40 0.95
0.669 0.905 0.025
0.677 0.913 0.031 0.063
0.685 0.921 0.037
0.08 0 7 0
0.003 7
Note:
1.Dimension D & E do not include interlead flash. 2.Dimension b does not include dambar protrusion/intrusion . 3.Controlling dimension : Millimeter 4.General appearance spec. should be based on final visual inspection spec.
A A2 See Detail F Seating Plane A1 y
L L1 Detail F
5. PCB layout please use the "mm".
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W83627THF/W83627THG
12. APPENDIX A : DEMO CIRCUIT
5 WDTO PLED GP31 GP30 GP26 GP25 GP24 GP23 7 VIN3 7 VIN2 7 VIN1 7 CPUVCORE IRRX IRTX RIB# DCDB# SOUTB SINB DTRB# RTSB# DSRB# CTSB# CASEOPEN# GP40 IO5V SLP_SX# PWRCTL# IO5V 4.7K PWROK IOBAT 7 7 7 7 VREF VTIN CPUTIN SYSTIN RSMRST# GP45 PSIN GP36 GP35 PANSWOUT# 5 5 For Wake Up Function 5 MDAT MCLK 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 U1 Keyboard & PS2 Mouse. 2 2 To Power supply for turn ON VCC. 5 Indicated the VCC is OK. 3 3 3 3 3,5 3 3 3 3 3 7
COMB & IR
4.7K R1
H/W MONITOR
R2
For VRD10's VID Control Don't need pull-up resistor
6 6 6 2 2 2 2 2 2 2 2 2 2
GP55 GP54 GP53 GP52 GP51 GP50 OVT# FANIN2 FANIN1 FANOUT2 FANOUT1 GP22 MSI MSO GPSA2 GPSB2 GPY1 GPY2 GPX2 GPX1 GPSB1 GPSA1
AVCC
MIDI PORT
GAME PORT
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
VTIN VREF CPUVCORE VIN1 VIN2 VIN3 GP23 GP24 GP25 GP26 GP30 GP31 PLED/GP32 WDTO/GP33 IRRX/GP34 IRTX GP35 RIB# DCDB# PEN48/SOUTB SINB DTRB# RTSB# DSRB# CTSB# GP36 CASEOPEN# GP40 VBAT SLP_SX#/GP41 PWRCTL#/GP42 PWROK/GP43 RSMRST#/GP44 GP45 PSIN/GP46 PSOUT#/GP47 MDAT MCLK
CPUTIN SYSTIN GP55 GP54 GP53 GP52 GP51 GP50 OVT# FANIN2 FANIN1 AVCC FANOUT2 FANOUT1 AGND GP22 MSI/GP21 MSO/IRQIN0/GP20 GPSA2/GP17 GPSB2/GP16 GPY1/GP15 GPY2/GP14 GPX2/GP13 GPX1//GP12 GPSB1/GP11 GPSA1/GP10
W83627THF
SUSLED/GP37 KDAT KCLK VSB KBRST GA20M BEEP RIA# DCDA# VSS PENKBC/SOUTA SINA PNPCSV/DTRA# HEFRAS/RTSA# DSRA# CTSA# VCC STB# AFD# ERR# INIT# SLIN# PD0 PD1 PD2 PD3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
SUSLED KDAT KCLK KBRST GA20M BEEP RIA# DCDA# SOUTA SINA DTRA# RTSA# DSRA# CTSA# IO5V STB# AFD# ERR# INIT# SLIN#
5 2 2 IOVSB C1 3 3 3,5 3 3,5 3,5 3 3 4 4 4 4 4 0.1UF
COMA
C2 .1UF
DRVDEN0 SMI#/IRQIN1 INDEX# MOA# FANIN3 DSA# FANOUT3 DIR# STEP# WD# WE# VCC TRAK0# WP# RDATA# HEAD# DSKCHG# CLKIN PME# VSS PCICLK LDRQ# SERIRQ LAD3 LAD2 LAD1 LAD0 VCC3V LFRAME# LRESET# SLCT PE BUSY ACK# PD7 PD6 PD5 PD4
AVCC
L1
FB
IO5V
Printer
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD[0..7] 4
JP1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 U2 IO5V 4 VCC O/P GND 3 2 5 5 5 PME# PCICLK LDRQ# SERIRQ LAD[0..3] 5 LFRAME# LRESET# LAD[0..3] IO5V 0.1UF IO3V C4 .1UF RWC# INDEX# MOA# DSA# DIR# STEP# WD# WE# TRAK0# WP# RDATA# HEAD# DSKCHG# 6 6 SMI# FANIN3 FANOUT3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
ACK# BUSY PE SLCT
4 4 4 4
C3
HEADER 17X2
|LINK |627THF_1.SCH |627THF_2.SCH |627THF_3.SCH |627THF_4.SCH |627THF_5.SCH |627THF_6.SCH |627THF_7.SCH
OSC 24M/48M Hz
LPC INTERFACE
LAD3 LAD2 LAD1 LAD0
Winbond Electronic Corp. Title W83627THF APPLICATION CIRCUIT Size B Date: Document Number W83627THF + FDC Wednesday, April 09, 2003 Sheet 1 of 7 Rev 0.1
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
OnNow or Wake_up function power
D1 IO5V 2 1N4148
VWAKE F1 VWAKE FUSE C5 10U R3 4.7K R4 4.7K L2 1 MDAT FB L3 J1 1 2 3 4 5 6 HEADER 6 2
JP2 KB/MS D2 IOVSB 1N4148
1
1
1
MCLK C6 47P C7 47P
FB
VWAKE CIRCUIT
PS2 MOUSE
BATTERY CIRCUIT
IOBAT BT1 BATTERY 3V R7 1K D3 1 1N4148 C8 0.1U 3 2 1 1
VWAKE R5 4.7K R6 4.7K L4 KDAT FB L5 KCLK C9 47P C10 47P FB C11 0.1U J2 1 2 3 4 5 6 HEADER 6
JP3:1-2 Clear CMOS 2-3 Enable ONNOW functions
JP3 HEAD3
KEYBOARD
GAME & MIDI PORT CIRCUIT
IO5V IO5V IO5V IO5V IO5V
R8 2.2K
R9 2.2K
R10 2.2K
R11 2.2K
L6 FB
P1 R12 2.2K 1 1 1 1 1 1 1 1 1 1 MSI GPSA2 GPSB2 GPY1 GPY2 MSO GPX2 GPX1 GPSB1 GPSA1 R16 2.2K R17 2.2K R13 2.2K R14 2.2K R15 2.2K 8 15 7 14 6 13 5 12 4 11 3 10 2 9 1 PRT
R18 1M
R19 1M
R20 1M
R21 1M
C12 0.01U C13 0.01U C14 0.01U C15 0.01U C16 0.01U
C17 0.01U
C18 0.01U
C19 0.01U
C20 0.01U
Winbond Electronic Corp. Title W83627THF APPLICATION CIRCUIT Size B Date: Document Number GAME & MIDI & KBC Wednesday, April 09, 2003 Sheet 2 of 7 Rev 0.1
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W83627THF/W83627THG
COM PORT
U3 IO5V 1,5 1,5 1,5 1 1 1 1 1 RTSA# DTRA# SOUTA RIA# CTSA# DSRA# SINA DCDA# RTSA# DTRA# SOUTA RIA# CTSA# DSRA# SINA DCDA# 20 16 15 13 19 18 17 14 12 11 VCC DA1 DA2 DA3 RY1 RY2 RY3 RY4 RY5 GND W83778 +12V DY1 DY2 DY3 RA1 RA2 RA3 RA4 RA9 -12V 1 5 6 8 2 3 4 7 9 10 IO+12V NRTSA NDTRA NSOUTA NRIA NCTSA NDSRA NSINA NDCDA IO-12V GND NRIA NDTRA NCTSA NSOUTA NRTSA NSINA NDSRA NDCDA 5 9 4 8 3 7 2 6 1 CONNECTOR DB9 1 IRRX IRTX P2
IR CONNECTOR
IO5V J3 1 2 3 4 5 CN2X5 6 7 8 9 10
COMA
(UARTA)
(SOP20)
1
U4 IO5V 1 1 1,5 1 1 1 1 1 RTSB# DTRB# SOUTB RIB# CTSB# DSRB# SINB DCDB# 20 16 15 13 19 18 17 14 12 11 VCC DA1 DA2 DA3 RY1 RY2 RY3 RY4 RY5 GND W83778 +12V DY1 DY2 DY3 RA1 RA2 RA3 RA4 RA9 -12V 1 5 6 8 2 3 4 7 9 10 IO+12V NRTSB NDTRB NSOUTB NRIB NCTSB NDSRB NSINB NDCDB IO-12V JP4 NDCDB NSOUTB GND NRTSB NRIB 1 3 5 7 9 2 4 6 8 10 NSINB NDTRB NDSRB NCTSB
HEADER 5X2
COMB
(UARTB)
(SOP20)
Winbond Electronic Corp. Title W83627THF APPLICATION CIRCUIT Size B Date: Document Number UART+IR Wednesday, April 09, 2003 Sheet 3 of 7 Rev 0.1
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
IO5V
D4 DIODE
8 7 6 5
8 7 6 5
8 7 6 5
PRT PORT
RP5 1 1 1 1 1 STB# AFD# INIT# SLIN# PD[0..7] PD[0..7] PD0 PD1 PD2 PD3 1 2 3 4 22 RP7 PD4 PD5 PD6 PD7 1 2 3 4 22 1 1 1 1 1 ERR# ACK# BUSY PE SLCT 8 7 6 5 1 2 3 4 22 RP6 8 7 6 5 8 7 6 5
RP1 2.7K 1 2 3 4 1 2 3 4
RP2 2.7K
RP3 2.7K 1 2 3 4 1 2 3 4
8 7 6 5 RP4 2.7K R22 2.7K
J4 NDP2 NDP15 NDP3 NDP4 NDP5 NDP6 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 DB25
NDP10 NDP11 NDP12 NDP13
C21 180P C30 180P
C22 180P C31 180P
C23 180P C32 180P
C24 180P C33 180P
C25 180P
C26 180P C34 180P
C27 180P C35 180P C36 180P
C28 180P C37 180P
C29 180P
Winbond Electronic Corp. Title W83627THF APPLICATION CIRCUIT Size B Date: Document Number PRINT PORT Wednesday, April 09, 2003 Sheet 4 of 7 Rev 0.1
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W83627THF/W83627THG
POWER ON SETTING PIN
S1 STREN HEFRAS PNPCSV1,3 PENKBC1,3 PEN48 1,3 1,3 GP42 RTSA# DTRA# SOUTA SOUTB 1 2 3 4 5 SW DIP-5 10 9 8 7 6
R23 4.7K R?(8P4RA1 1 8 2 7 3 6 4 5 4.7K
IOVSB IO5V
SUSPEND LED CIRCUIT
IOVSB R24 150 D5 Q1 2N3904 SUSLED R25 4.7K
POWER ON SETTING PIN
RP8 HEFRAS 1,3 PNPCSV 1,3 PENKBC 1,3 PEN48 1,3 RTSA# DTRA# SOUTA SOUTB 1 2 3 4 4.7K 8 7 6 5
1
SUSLED
IO5V
POWER LED CIRCUIT
R26 150 IO5V LED R27 4.7K D6 Q2 2N3904
1
PLED
PANEL SWITCH
IOVSB 1 PSIN R29 10K R28 1K JP5 1 2 HEADER 2 C38 0.1U
0
RTSA# DTRA# SOUTA SOUTB 2E DEFAULT KBC DISABLE CLK 24M
1
4E ALL 0 KBC ENABLE CLK 48M PIN18 INPUT CLK VALUE I/O CONFIGURATION ADDRESS I/O PORT BASE DEFAULT VALUE
Signal Pullhigh IO3VSB
RP9 1 1 1 1 PME# PANSWOUT# RSMRST# PWRCTL# 1 2 3 4 4.7K IO3V RP10 1 1 1 LDRQ# LFRAME# SERIRQ 1 2 3 4 4.7K IO3V RP11 1 LAD[0..3] 1 2 3 4 4.7K 8 7 6 5 8 7 6 5 8 7 6 5
IOVSB
Winbond Electronic Corp. Title W83627THF APPLICATION CIRCUIT Size B Date: Document Number Power setting Wednesday, April 09, 2003 Sheet 5 of 7 Rev 0.1
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
Circuit for DC FAN speed control
Type 1 : Transistor 2SC5706
Type 2 : PMOS CEB05P03
IO+12V IO+12V IO+12V Q3 NPN 2SC5706 1N4148 1 LM358 4 R34 D7 R30 4.7K JP6 3 2 1 HEADER 3 R31 FANIN1 27K R33 JP7 10K R36 20K R39 20K 28K 28K R38 3 2 1 HEADER 3 1 IO+12V IO+12V 4 6 5 U5B LM358 8 + 7 470K D 1N4148 D8 R32 4.7K R35 FANIN2 27K R37 10K 1 R57 G Q4 CEB05P03 S IO+12V
1
FANOUT1
3 2
+ -
Type 3 : LDO LM1117
IO+12V
8
U5A
1
FANOUT2
U6 2
Note :
IO+12V LM1117 1N4148 D9 R40 4.7K JP8 3 2 1 HEADER 3 R41 FANIN3 27K R42 10K 1
1 IO+12V
ADJ OUT
IN
1. Transistor,MOSFET,LDO We suggest TO-252 or TO-262 type of package 2. Use 2SC5706, Max. FANVCC 3. Use CEB05P03, Max. FANVCC is 10.2V is 12V
1 FANOUT3
3 2
+ -
8
U7A 1 LM358
4
3
4. Use LM1117, Max. FANVCC max is 10.8V
R43
R44 20K
28K
Winbond Electronic Corp. Title W83627THF APPLICATION CIRCUIT Size B Date: Document Number FAN Control Wednesday, April 09, 2003 Sheet 6 of 7 Rev 0.1
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W83627THF/W83627THG
Temperature Sensing
RT1 VREF R45 10K 1% RT2 R46 1 VTIN 10K 1% THERMISTOR R48 4.7K THERMISTOR IO5V
1
SYSTIN
t
t
R47 100 LS1
R49 1 CPUTIN
30K C39 3300P
CPUD+
1 BEEP FROM CPU'S THERM DIODE
SPEAKER Q5 NPN
CPUD-
R50 IOBAT 2M CASEOPEN# 1
Voltage Sensing
S2 SW SPST R51 CPUVCO 10K R52 IO+12V 28K 1% R55 1 VREF 56K 1% 232K 1% VIN2 1 10K 1% VIN1 R56 IO-12V 1 R53 IO3V 10K 1% R54 VIN3 1 CPUVCORE 1
Winbond Electronic Corp. Title W83627THF APPLICATION CIRCUIT Size B Date: Document Number Temperature+Voltage sensing Wednesday, April 09, 2003 Sheet 7 of 7 Rev 0.1
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
13. W83627THF VERSION CHANGE NOTICE 1
Feature Brief W83627THF : LPC I/F + FDC + 2* UART + Parallel Port + KBC + Game Port + MIDI Port + ACPI + Power failure + Hardware Monitor + GPIO + VRD10.0
Description This version change notice is for the W83627THF to be changed from C to E. The contents:
1. 2. 3.
The E version can directly replace C version without any circuit or S/W change except Fan Control Function. Chip ID is changed from 0x8283h to 0x8285h. SYSFANOUT (Pin 116), CPUFANOUT (Pin 115) and AUXFANOUT (Pin 7) are revised as the following table. They are configured by CR[F0h] bit4 ~ bit6 of Logical Device B.
C VERSION E VERSION
Pin
Function
Default
Function
Default
115-CPUFANOUT 116-SYSFANOUT 7-AUXFANOUT 4.
DC fan out DC fan out DC fan out
DC fan out DC fan out DC fan out
PWM/DC fan out PWM/DC fan out PWM/DC fan out
PWM fan out DC fan out DC fan out
The programming method is described in W83627THF APN04.
W83627THF Version Change Notices List
DATE VERSION REMARK
1
03/04/2004
VCN1
Release Notice for C version to E version.
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W83627THF/W83627THG
14. W83627THF APPLICATION NOTICE 4
Feature Brief
(FOR E VERSION)
W83627THF : LPC I/F + FDC + UART*2 + Parallel Port + KBC + Game Port + MIDI Port + ACPI + Power failure + Hardware Monitor + GPIO + VRD10.0
Description
W83627THF Version E provides two controllable methods for Fan speed control. One is PWM duty cycle output and the other is DC voltage output. Either PWM or DC output can be programmed at CR[F0h] bit4 ~ bit6 of Logical Device B.
CR[F0h] of Logical Device B
BIT DESCRIPTION
AUXFANOUT output mode selection. 6 :0, DC voltage. (default) :1, PWM duty cycle. CPUFANOUT output mode selection. 5 :0, DC voltage. :1, PWM duty cycle. (default) SYSFANOUT output mode selection. 4 :0, DC voltage. (default) :1, PWM duty cycle.
1. PWM Duty Cycle Output
The duty cycle of PWM can be programmed by a 8-bit registers which are defined in the Bank0 Index 01h, Index03h and Index 11h of H/W Monitor block. The default duty cycle is set to 100%, that is, the default 8-bit registers is set to FFh. The expression of duty can be represented as follows.
Dutycycle(%) =
Programmed 8 - bit Register Value x 100% 255
The PWM clock frequency also can be program and defined in the Bank0 Index 00h, Index 02h and Index 10h of H/W Monitor block.
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
2. DC Voltage Output
The W83627THF has a 4 bit DAC which produces 0 to 5 volts DC output that provides maximum 3 sets for fan speed control. The analog output can be programmed in the Bank0 Index 01h, Index 03h and Index 11h of H/W Monitor block. The default value is 0xFY,Y is reserved nibble, that is default output value is nearly 5V. The expression of output voltage can be represented as follow ,
Output Voltage (V) = AVCC x
Programmed 4 - bit Register Value 16
The application circuit is shown as follow,
This application circuit used Winbond W83391TS Pre-Driver to control Fan speed. It can support both PWM and DC output.
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W83627THF/W83627THG
Difference between C and E version :
A. Pin Description SYSFANOUT CPUFANOUT AUXFANOUT 116 115 7 OUT12 Fan speed control. Use the Pulse Width Modulation (PWM) to control the Fan's RPM. AOUT Fan speed control. Output analog voltage level to control the Fan's speed.
B. Fan Speed Control Registers
14.1
SYSFANOUT PWM Output Frequency Configuration Register - Index 00h
00h 01h Read/Write 8 bits
7 6 5 4 3 2 1 0
Register Location: Power on Default Value: Attribute: Size:
PWM_SCALE1
PWM_CLK_SEL1
The register is meaningful when SYSFANOUT be programmed as PWM output.
Bit 7: SYSFANOUT PWM Input Clock Source Select. This bit selects the clock source of PWM output f requency. Set to 0, select 24 MHz. Set to 1, select 180 KHz. Bit 6-0: SYSFANOUT PWM Pre-Scale divider. This is the divider of clock source of PWM output frequency. The maximum divider is 128 (7Fh). This divider should not be set to 0. 01h : divider is 1 02h : divider is 2 03h : divider is 3 :
:
the formula is
PWM output frequency =
Input Clock 1 Pre_Scale Divider 256
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
14.2 SYSFANOUT Output Value Select Register - Index 01h
01h FFh Read/Write 8 bits
7 6 5 4 3 2 1 0
Register Location: Power on Default Value: Attribute: Size:
SYSFANOUT Value
(1)If SYSFANOUT be programmed as PWM output (CR[F0h] of LD B bit4 is 1)
Bit 7-0: SYSFANOUT PWM Duty Cycle. Write FFh, SYSFANOUT is always logical High which means duty cycle is 100%. Write 00h, SYSFANOUT is always logical Low which means duty cycle is 0%.
Note. XXh: PWM Duty Cycle output percentage is (XX/255*100%) during one cycle. (2)If SYSFANOUT be programmed as DC Voltage output (CR[F0h] of LD B bit4 is 0)
Bit 7-4: SYSFANOUT voltage control. Bit 3-0: Reserved.
OUTPUT Voltage = AVCC *
FANOUT 16
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W83627THF/W83627THG
If AVCC= 5V , output voltage table is
BIT 7 BIT 6 BIT 5 BIT 4 OUTPUT VOLTAGE BIT 7 BIT 6 BIT 5 BIT 4 OUTPUT VOLTAGE
0 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 0.31 0.63 0.97 1.25 1.56 1.88 2.19
1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
2.50 2.81 3.13 3.44 3.75 4.06 4.38 4.69
Table 7.4 .
Note. The accuracy of FANOUT voltage is +/- 0.16 V.
14.3
CPUFANOUT PWM Output Frequency Configuration Register - Index 02h
02h 01h Read/Write 8 bits
7 6 5 4 3 2 1 0
Register Location: Power on Default Value: Attribute: Size:
PWM_SCALE2
PWM_CLK_SEL2
The register is meaningful when CPUFANOUT be programmed as PWM output.
Bit 7: CPUFANOUT PWM Input Clock Source Select. This bit selects the clock source of PWM output frequency. Set to 0, select 24 MHz. Set to 1, select 180 KHz. Bit 6-0: CPUFANOUT PWM Pre-Scale divider. This is the divider of clock source of PWM output frequency. The maximum divider is 128 (7Fh). This divider should not be set to 0.
Publication Release Date: September 26, 2006 Revision 1.2
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W83627THF/W83627THG
01h : divider is 1 02h : divider is 2 03h : divider is 3 : : the formula is
PWM output frequency =
Input Clock 1 Pre_Scale Divider 256
14.4
CPUFANOUT Output Value Select Register - Index 03h
03h FFh Read/Write 8 bits
7 6 5 4 3 2 1 0
Register Location: Power on Default Value: Attribute: Size:
CPUFANOUT Value
(1)If CPUFANOUT be programmed as PWM output (CR[F0h] of LD B bit5 is 1)
Bit 7-0: CPUFANOUT PWM Duty Cycle. Write FFh, CPUFANOUT duty cycle is 100%. Write 00h, CPUFANOUT duty cycle is 0%.
Note. XXh: PWM Duty Cycle output percentage is (XX/255*100%) during one cycle. (2)If CPUFANOUT be programmed as DC Voltage output (CR[F0h] of LD B bit5 is 0)
Bit 7-4: CPUFANOUT voltage control. Bit 3-0: Reserved.
OUTPUT Voltage = AVCC * Note. See the Table 7.4
FANOUT 16
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W83627THF/W83627THG
14.5 FAN Configuration Register I - Index 04h
04h 00h Read/Write 8 bits
Register Location: Power on Default Value: Attribute: Size:
7
6
5
4
3
2
1
0
Reserved Reserved SYSFANOUT_Mode SYSFANOUT_Mode CPUFANOUT_Mode CPUFANOUT_Mode Reserved Reserved
Bit 7-6: Reserved. Bit 5-4: CPUFANOUT mode control. Set 00, CPUFANOUT is as Manual Mode. (Default). Set 01, CPUFANOUT is as Thermal Cruise Mode. Set 10, CPUFANOUT is as Fan Speed Cruise Mode. Set 11, reserved and no function. Bit 3-2: SYSFANOUT mode control. Set 00, SYSFANOUT is as Manual Mode. (Default). Set 01, SYSFANOUT is as Thermal Cruise Mode. Set 10, SYSFANOUT is as Fan Speed Cruise Mode. Set 11, reserved and no function. Bit 1-0: Reserved.
14.6
SYSFANOUT Stop Value Register - Index 08h
08h 01h Read/Write 8 bits
Register Location: Power on Default Value: Attribute: Size:
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
7
6
5
4
3
2
1
0
SYSFANOUT Stop Value
When at Thermal Cruise mode, SYSFANOUT value will decrease to this register value. This register should be written a non-zero minimum stop value.
14.7
CPUFANOUT Stop Value Register - Index 09h
09h 01h Read/Write 8 bits
7 6 5 4 3 2 1 0
Register Location: Power on Default Value: Attribute: Size:
CPUFANOUT Stop Value
When at Thermal Cruise mode, CPUFANOUT value will decreases to this register value. This register should be written a non-zero minimum stop value.
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W83627THF/W83627THG
14.8 SYSFANOUT Start-up Value Register - Index 0Ah
0Ah 01h Read/Write 8 bits
7 6 5 4 3 2 1 0
Register Location: Power on Default Value: Attribute: Size:
SYSFANOUT Start-up Value
When at Thermal Cruise mode, SYSFANOUT value will increase from 0 to this register value to provide a minimum value to turn on the fan.
14.9
CPUFANOUT Start-up Value Register - Index 0Bh
0Bh 01h Read/Write 8 bits
7 6 5 4 3 2 1 0
Register Location: Power on Default Value: Attribute: Size:
CPUFANOUT Start-up Value
When at Thermal Cruise mode, CPUFANOUT value will increase from 0 to this register value to provide a minimum value to turn on the fan.
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
14.10 SYSFANOUT Stop Time Register - Index 0Ch
Register Location: Power on Default Value: Attribute: Size:
7 6 5
0Ch 3Ch Read/Write 8 bits
4 3 2 1 0
SYSFANOUT Stop Time
When at Thermal Cruise mode, this register determines the time of which SYSFANOUT value is from stop value to 0. (1)When at PWM output: The unit of this register is 0.1 second. The default time is 6 seconds. (2)When at DC Voltage output: The unit of this register is 1.6 second. The default time is 96 seconds.
14.11 CPUFANOUT Stop Time Register - Index 0Dh
Register Location: Power on Default Value: Attribute: Size:
7 6
0Dh 3Ch Read/Write 8 bits
5 4 3 2 1 0
CPUFANOUT Stop Time
When at Thermal Cruise mode, this register determines the time of which CPUFANOUT value is from stop value to 0. (1)When at PWM output: The unit of this register is 0.1 second. The default time is 6 seconds. (2)When at DC Voltage output: The unit of this register is 1.6 second. The default time is 96 seconds.
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W83627THF/W83627THG
14.12 Fan Output Step Down Time Register - Index 0Eh
Register Location: Power on Default Value: Attribute: Size:
7 6 5
0Eh 0Ah Read/Write 8 bits
4 3 2 1 0
FANOUT Value Step Down Time
This register determines the speed of FANOUT decreasing its value in Smart Fan Control mode. (1)When at PWM output: The unit of this register is 0.1 second. The default time is 1 seconds. (2)When at DC Voltage output: The unit of this register is 1.6 second. The default time is 16 seconds.
14.13 Fan Output Step Up Time Register - Index 0Fh
Register Location: Power on Default Value: Attribute: Size:
7 6 5
0Fh 0Ah Read/Write 8 bits
4 3 2 1 0
FANOUT Value Step Up Time
This register determines the speed of FANOUT increasing the its value in Smart Fan Control mode. (1)When at PWM output: The unit of this register is 0.1 second. The default time is 1 seconds. (2)When at DC Voltage output: The unit of this register is 1.6 second. The default time is 16 seconds.
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
14.14 AUXFANOUT PWM Output Frequency Configuration Register - Index 10h
Register Location: Power on Default Value: Attribute: Size:
7
10h 01h Read Only 8 bits
6 5 4 3 2 1 0
PWM_SCALE3
PWM_CLK_SEL3
The register is meaningful when AUXFANOUT be programmed as PWM output.
Bit 7: AUXFANOUT PWM Input Clock Source Select. This bit selects the clock source of PWM output frequency. Set to 0, select 24 MHz. Set to 1, select 180 KHz. Bit 6-0: AUXFANOUT PWM Pre-Scale divider. This is the divider of clock source of PWM output frequency. The maximum divider is 128 (7Fh). This divider should not be set to 0. 01h : divider is 1 02h : divider is 2 03h : divider is 3 : : the formula is
PWM output frequency =
Input Clock 1 Pre_Scale Divider 256
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W83627THF/W83627THG
14.15 AUXFANOUT Output Value Select Register - Index 11h
Register Location: Power on Default Value: Attribute: Size:
7 6
11h FFh Read/Write 8 bits
5 4 3 2 1 0
AUXFANOUT Value
(1)If AUXFANOUT be programmed as PWM output (CR[F0h] of LD B bit6 is 1)
Bit 7-0: AUXFANOUT PWM Duty Cycle. Write FFh, AUXFANOUT duty cycle is 100%. Write 00h, AUXFANOUT duty cycle is 0%.
Note. XXh: PWM Duty Cycle output percentage is (XX/255*100%) during one cycle. (2)If AUXFANOUT be programmed as DC Voltage output CR[F0h] of LD B bit6 is 0)
Bit 7-4: AUXFANOUT voltage control. Bit 3-0: Reserved.
OUTPUT Voltage = AVCC * Note. See the Table 7.4
FANOUT 16
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
14.16 FAN Configuration Register II - Index 12h
Register Location: Power on Default Value: Attribute: Size:
7 6
12h 00h Read/Write 8 bits
5 4 3 2 1 0
Reserved AUXFANOUT_Mode AUXFANOUT_Mode AUXFANOUT_MIN_Value CPUFANOUT_MIN_Value SYSFANOUT_MIN_Value Reserved Reserved
Bit 7-6: Reserved Bit 5: Set 1, SYSFANOUT value will decrease to and keep the value set in Index 08h when temperature goes below target range. This is to maintain the fan speed in a minimum value. Set 0, SYSFANOUT value will decrease to 0 when temperature goes below target range. Bit 4: Set 1, CPUFANOUT value will decrease to and keep the value set in Index 09h when temperature goes below target range. This is to maintain the fan speed in a minimum value. Set 0, CPUFANOUT value will decrease to 0 when temperature goes below target range. Bit 3: Set 1, AUXFANOUT value will decrease to and keep the value set in Index 17h when temperature goes below target range. This is to maintain the fan speed in a minimum value. Set 0, AUXFANOUT value will decrease to 0 when temperature goes below target range. Bit 2-1: AUXFANOUT mode control. Set 00, AUXFANOUT is as Manual Mode. (Default). Set 01, AUXFANOUT is as Thermal Cruise Mode. Set 10, AUXFANOUT is as Fan Speed Cruise Mode. Set 11, reserved and no function. Bit 0: Reserved.
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W83627THF/W83627THG
14.17 AUXFANOUT Stop Value Register - Index 15h
Register Location: Power on Default Value: Attribute: Size:
7 6
15h 01h Read/Write 8 bits
5 4 3 2 1 0
AUXFANOUT Stop Value
When at Thermal Cruise mode, AUXFANOUT value will decrease to this register value. This register should be written a non-zero minimum stop value.
14.18 AUXFANOUT Start-up Value Register - Index 16h
Register Location: Power on Default Value: Attribute: Size:
7 6 5
16h 01h Read/Write 8 bits
4 3 2 1 0
AUXFANOUT Start-up Value
When at Thermal Cruise mode, AUXFANOUT value will increase from 0 to this register value to provide a minimum value to turn on the fan.
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Publication Release Date: September 26, 2006 Revision 1.2
W83627THF/W83627THG
14.19 AUXFANOUT Stop Time Register - Index 17h
Register Location: Power on Default Value: Attribute: Size:
7 6
17h 3Ch Read/Write 8 bits
5 4 3 2 1 0
AUXFANOUT Stop Time
When at Thermal Cruise mode, this register determines the time of which AUXFANOUT value is from stop value to 0. (1)When at PWM output: The unit of this register is 0.1 second. The default time is 6 seconds. (2)When at DC Voltage output: The unit of this register is 1.6 second. The default time is 96 seconds.
W83627THF/W83627THG Application Notice List
DATE VERSION REMARK
1 2 3 4
03/01/10 03/04/08 04/01/16 09/26/2006
APN1 APN2 APN3 APN4
New release for W83627THF. For W83627THF C version W83627THF Power On Cycle Issue For W83627THF E version
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W83627THF/W83627THG
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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Publication Release Date: September 26, 2006 Revision 1.2

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